byuccl / bfasst Goto Github PK

Tools for FPGA Assurance Flows

License: Apache License 2.0

Shell 0.01% Stata 0.01% Tcl 1.02% Verilog 19.56% VHDL 76.55% Python 0.25% Makefile 0.01% Pascal 0.01% SystemVerilog 0.49% C++ 0.19% AGS Script 1.93% Mustache 0.01%

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bfasst's Issues

run_design.py doesn't print to stdout

There is a --quiet option, but even when this isn't set, the command produces no output while it is running. Is there a reason for this? The old behavior printed the stdout of each tool.

Statuses aren't printed correctly in run_experiment.py

When using run_experiment.py, Status objects are printed incorrect (it shows the Status type twice):

(.venv) jgoeders@Jeff:~/bfasst$ python scripts/run_experiment.py experiments/tests/phy_netlist_structural_cmp.yaml 
Running 16 designs 
byu/Sout_reg                Transform Error (Transform Error (Unhandled primitive INBUF_EN))
byu/UpDownButtonCount       Transform Error (Transform Error (Unhandled primitive INBUF_EN))
byu/alu                     Transform Error (Transform Error (Unhandled primitive INBUF_EN))
byu/buttoncount             Transform Error (Transform Error (Unhandled primitive CFF))
byu/calc                    Transform Error (Transform Error (Unhandled primitive INBUF_EN))
byu/debouncer               Transform Error (Transform Error (Unhandled primitive BFF))
byu/lightWave               Transform Error (Transform Error (Unhandled primitive OUTBUF))
byu/mux8to1                 Transform Error (Transform Error (Unhandled primitive PAD))
byu/oneshot                 Transform Error (Transform Error (Unhandled primitive PAD))
byu/regfile                 Transform Error (Transform Error (Unhandled primitive AFF))
byu/riscvSimpleDatapath     Transform Error (Transform Error (Unhandled primitive PAD))
byu/rx                      Transform Error (Transform Error (Unhandled primitive PAD))
byu/seven_segment           Transform Error (Transform Error (Unhandled primitive PAD))
byu/shiftReg                Transform Error (Transform Error (Unhandled primitive A5FF))
byu/stopwatch               Transform Error (Transform Error (Unhandled primitive DFF))
byu/tx                      Transform Error (Transform Error (Unhandled primitive INBUF_EN))

Caedm/compile_results.py uses Python2?

Is this file supposed to use python2? The #! and the print call seems to suggest so. Any reason why it can't be ran in python3?

Run Experiment is not actually killed by ctrl+c or by killing master terminal.

Not running Vivado with multiple system verilog modules

Now there's an issue where any extra system verilog files from the base folder are not being recognized. My guess is they are not being written to correctly in vivado.py in the write_tcl function. (It looks like the portion that says for hdl_file in design.system_verilog_file_paths stream.write(...), the design.system_verilog_file_paths array is empty. I'm wondering if it's not being correctly added to.)

Here's the traceback:

Traceback (most recent call last):
  File "/home/edvenson/bfasst/scripts/run_design.py", line 89, in <module>
    main(design_path, args.flow, args.error_flow, args.flow_args)
  File "/home/edvenson/bfasst/scripts/run_design.py", line 28, in main
    status = run_flow(design, flow, flow_args, build_dir)
  File "/home/edvenson/bfasst/scripts/bfasst/flows.py", line 104, in run_flow
    return flow_fcn(design, flow_args, build_dir)
  File "/home/edvenson/bfasst/scripts/bfasst/flows.py", line 290, in flow_xilinx_yosys_waveform
    status = vivado_synth(design, build_dir, flow_args[FlowArgs.SYNTH])
  File "/home/edvenson/bfasst/scripts/bfasst/flows.py", line 142, in vivado_synth
    return synth_tool.create_netlist(design)
  File "/home/edvenson/bfasst/scripts/bfasst/synth/vivado.py", line 55, in create_netlist
    status = self.get_prev_run_status(
  File "/home/edvenson/bfasst/scripts/bfasst/tool.py", line 61, in get_prev_run_status
    status = tool_product.check_log_fcn(tool_product.log_path)
  File "/home/edvenson/bfasst/scripts/bfasst/synth/vivado.py", line 177, in check_synth_log
    return Status(SynthStatus.ERROR, match.group(1).strip())
  File "/home/edvenson/bfasst/scripts/bfasst/status.py", line 93, in __init__
    raise BfasstException(status, f"{msg_map[status]}{self.msg}")
bfasst.status.BfasstException: !! Synth Error ([Synth 8-439] module 'regfile' not found [/home/edvenson/bfasst/examples/byu/riscv_final/riscv_final.sv:513])

Note: If I run bfasst on system verilog designs that don't rely on any other modules, it works correctly. It's only when there are other system verilog files that there is an issue.

find master pcf for Lattice Parts

Remove bfasst/error_injection and all references to it

Remove the old bfasst error injector from the project, now that we have integrated a new one in that uses spydrnet. The old injector is found at bfasst/error_injection. DO NOT REMOVE THE INJECTOR FOUND AT bfasst/transform

Remove the tool
Remove the tool_wrapper methods that instance the tool
Remove the flows that call the tool_wrapper methods
Clean up associated imports
Remove the alias from the import for the new error injector in flows.py and unalias the instance of the new error injector

Add weekly CI

I would like to have a weekly CI where we run some of our larger designs (ooc and base) through some of our flows. At minimum this would just be the xilinx flow.

Add CI test for WaFoVe

Missing YOSYS_INSTALL_DIR constant

scripts/bfasst/synth/yosys.py:33:25: E1101: Module 'bfasst.config' has no 'YOSYS_INSTALL_DIR' member (no-member)
From what I see, neither the paths.py or config.py has this variable.

ooc weekly tests failing on ooc/ahbjtag

https://github.com/byuccl/bfasst/actions/runs/5366872955/jobs/9736552643#step:5:44

Unable to synthesize .sv files (xilinx_conformal_impl flow)

Note: My latest PR should fix this issue, if it gets merged feel free to just resolve this issue.

Issue

I just tried out run_design.py on the master branch to debug something and I found that any .sv files I'm using can't synthesize anymore. It seems that recent changes to design.py caused this. The design returned from design.py is always assumed to be a verilog file when it could be a system verilog file or a vhd file.

Traceback

Traceback (most recent call last):
  File "/home/edvenson/bfasst/scripts/run_design.py", line 89, in <module>
    main(design_path, args.flow, args.error_flow, args.flow_args)
  File "/home/edvenson/bfasst/scripts/run_design.py", line 28, in main
    status = run_flow(design, flow, flow_args, build_dir)
  File "/home/edvenson/bfasst/scripts/bfasst/flows.py", line 104, in run_flow
    return flow_fcn(design, flow_args, build_dir)
  File "/home/edvenson/bfasst/scripts/bfasst/flows.py", line 290, in flow_xilinx_yosys_waveform
    status = vivado_synth(design, build_dir, flow_args[FlowArgs.SYNTH])
  File "/home/edvenson/bfasst/scripts/bfasst/flows.py", line 142, in vivado_synth
    return synth_tool.create_netlist(design)
  File "/home/edvenson/bfasst/scripts/bfasst/synth/vivado.py", line 58, in create_netlist
    pathlib.Path(__file__).stat().st_mtime, design.last_modified_time()
  File "/home/edvenson/bfasst/scripts/bfasst/design.py", line 190, in last_modified_time
    return max(os.path.getmtime(f) for f in (self.yaml_path, self.top_file_path))
  File "/home/edvenson/bfasst/scripts/bfasst/design.py", line 190, in <genexpr>
    return max(os.path.getmtime(f) for f in (self.yaml_path, self.top_file_path))
  File "/usr/lib/python3.8/genericpath.py", line 55, in getmtime
    return os.stat(filename).st_mtime
FileNotFoundError: [Errno 2] No such file or directory: '/home/edvenson/bfasst/examples/byu/riscv_final/riscv_final.v'

The command I ran to do this was python /home/edvenson/bfasst/scripts/run_design.py bfasst/examples/byu/riscv_final xilinx_conformal_impl

Results of testing

From what I can see, the problem is that the default top_file_path is a verilog file and the other file path arrays are completely empty when using a system_verilog file. So, when calling design.top_file_path, it returns <path>/<design>.v rather than <path>/<design>.sv
Line 158 of find_top_file() seems to always return the verilog version of the top_file since top_paths is equal to an array of verilog, system_verilog, and vhd files.
I opened a PR that fixes this issue by always returning whatever is filtered from the list of top_paths rather than returning the verilog file in top_paths

Tool class should take design in init

We spend a lot of time passing around design objects. They could just be saved in tool.design on init of Tool object.

Add more primative support to xilinx_phys_netlist.py

Check whether MUXF7 pins can be reordered #132
Check if CARRY4 pins can be swapped #132
BUFG needs to be replaced with BUFGCTRL #140

Test physical netlist / structural matching with a design containing a BRAM

Consistency with BfasstException

It looks like BfasstException was added to the code base, but I'm not sure we are using it consistently. In some cases it looks like we are raising exceptions, and in others we are returning error statuses:

        # Run Icecube 2 LSE synthesis
        try:
            status = self.run_sythesis(prj_path, log_path)
        except BfasstException as e:
            # If generic error, see if log has something more specific
            if e.error == OptStatus.ERROR:
                new_status = self.check_opt_log(log_path)
                return new_status
            raise e

Move Flows To Classes

In order to allow for easier parallel processing in run experiment, it would be good if flows were classes instead.

Create Flow abstract class with abstract run() function.
Moves flows to their own class (also absorb tool wrappers into flows (although xilinx_ooc will be a subflow)).
Create exceptions for each tool that inherit from BfasstException. Stop returning statuses for tools and instead raise exceptions
Edit Status class so that it only relates to flows (no exception raising). Flows will return a status. The Flow.run() will have one try catch clause for all the tools that catches the parent BfassException, and passes the exception type to a failed status.

Conformal not finding modules that are being used in experiment unless module is included in top file.

This is a conformal log of a comparison of the ooc EX_stage before and after going through yosys synthesis. The log shows that the top file EX_stage.v is instancing the alu module which conformal can't find for some reason. The module in mips_16_defs.v is included in the EX_stage.v with an include statement. This may be what was causing the redefinition errors that were occurring before when I was running yosys synths because when I include the alu.v file in the EX_stage.v I receive a redefinition error once again. If I comment out the include_all_verilog_files: yes line in the design.yaml file for this experiment then It goes away.

Speed up environment setup in CI through local cache/environment

Problem when running yosys synth flows

When calling the yosys_synth function in flows.py the design object does not have a full_path attribute. AttributeError: 'Design' object has no attribute 'full_path'

Missing steps from README

Currently, the readme doesn't include mentions of installing bfasst as a package.

Reverse_bit_tool attribute error

I've tried running several flows using python3 scripts/run_design.py examples/byu/alu xilinx_yosys_impl (replacing the last part with other flow names) and whenever it reaches status = xray_rev(design, build_dir, flow_args) it throws an error at line 21 in scripts/bfasst/reverse_bit/base.py where it says AttributeError: 'collections.defaultdict' object has no attribute 'read'. I'm running this on the current commit from main in a virtual environment. Any thoughts?

CI fails with java.lang.RuntimeException: ERROR: Failed to reliably download file

The CI fails about half the time with an error downloading a file.
For example:

java.lang.RuntimeException: ERROR: Failed to reliably download file: data/devices/artix7/xc7a200t_db.dat

This happens while running experiments, not setting up the environment, which is unexpected, because the Rapidwright files are downloaded during environment setup. Not sure why files would be downloaded during the experiment run.

Add error injector script to test physical netlist / struct compare

Current physical netlist + structural compare flow:

bfasst/bfasst/flows.py

Line 191 in cb2aeae

def flow_xilinx_phys_netlist_cmp(design, flow_args, build_dir):

We would like a new flow that follows all of these same steps, except that before structural compare, it takes the "reversed" netlist (the one produced by xray_rev) and injects some modification before passing it to the structural comparison.

We would then want to repeat this injection many times (say 100 times) injecting a different random modification each time.

Injection types:

Pick random LUT, flip random bit in INIT
Pick random instance input pin and drive it from another random wire

These random choices should be seeded by a hard-coded value (could be overridden by command line flow argument), such that the chosen injection points are deterministic (ie repeatable)

Improper function calls

In the file flows.py there are several calls to bfasst.compare.conformal.Conformal_CompareTool() without specifying a vendor. From what I can tell, Vendor is a required arg. This happens on line 98, 261, 341, and 381. (For commit 742bfe2). Am I missing something?

Physical netlist: GND signal generated by a LUT

There is an issue where a GND signal generated by a LUT is not added to the physical netlist.

Example: UpDownButtonCount
CARRY4 \count_i_reg[12]_i_6

Structural compare needs a final verification step?

bfasst/bfasst/compare/structural.py

Lines 100 to 103 in 37c7ddd

    
           # TODO: After establishing mapping, verify equivalence 
        
           # Basically make sure all outputs are mapped, and then everything is identical 
        
           # Maybe this will already be guaranteed by the mapping algorithm? ...good to 
        
           # double check.

WaFoVe prints errors during installation inside setup_env action

While running wafove during environment setup, several errors are printed. The unit test still seems to pass, but it seems like these errors shouldn't happen?

/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/WaFoVe/wafove/testing/alu_test/alu_impl.v:5971: error: Unknown module type: LUT6
/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/WaFoVe/wafove/testing/alu_test/alu_impl.v:5981: error: Unknown module type: LUT6
/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/WaFoVe/wafove/testing/alu_test/alu_impl.v:5991: error: Unknown module type: LUT6
670 error(s) during elaboration.
*** These modules were missing:
        CARRY4 referenced 20 times.
        GND referenced 1 times.
        IBUF referenced 68 times.
        LUT2 referenced 88 times.
        LUT3 referenced 20 times.
        LUT4 referenced 53 times.
        LUT5 referenced 70 times.
        LUT6 referenced 315 times.
        OBUF referenced 33 times.
        VCC referenced 1 times.
***
/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/WaFoVe/wafove/testing/../out/dsn: Unable to open input file.
mv: cannot stat 'test.vcd': No such file or directory
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
VCD info: dumpfile test.vcd opened for output.
....
----------------------------------------------------------------------
Ran 9 tests in 12.482s
OK

Compare tool base constructor should take two netlists as arguments

Right now compare tools are hard-coded to use certain netlists in the design object (eg design.impl_netlist). Instead it should be controlled by the flow and passed to the tool constructor.

VHDL OOC designs fail to compile due to missing packages

ooc/ahbctrl                       !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'stdlib' not found in library 'grlib' [bfasst/designs/ooc/ahbctrl/ahbctrl.vhd:31]))
ooc/ahbjtag                       !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'amba' not found in library 'grlib' [bfasst/designs/ooc/ahbjtag/ahbjtag.vhd:30]))
ooc/ahbuart                       !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'amba' not found in library 'grlib' [bfasst/designs/ooc/ahbuart/ahbuart.vhd:30]))
ooc/apbctrl                       !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'gencomp' not found in library 'techmap' [bfasst/designs/ooc/apbctrl/config.vhd:6]))
ooc/dsu3                          !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'gencomp' not found in library 'techmap' [bfasst/designs/ooc/dsu3/config.vhd:6]))
ooc/grethm                        !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'gencomp' not found in library 'techmap' [bfasst/designs/ooc/grethm/config.vhd:6]))
ooc/irqmp                         !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'gencomp' not found in library 'techmap' [bfasst/designs/ooc/irqmp/config.vhd:6]))
ooc/leon3s                        !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'gencomp' not found in library 'techmap' [bfasst/designs/ooc/leon3s/config.vhd:6]))
ooc/mctrl                         !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'gencomp' not found in library 'techmap' [bfasst/designs/ooc/mctrl/config.vhd:6]))
ooc/spimctrl                      !! Synth Error (!! Synth Error ([Synth 8-4169] error in use clause: package 'gencomp' not found in library 'techmap' [bfasst/designs/ooc/spimctrl/config.vhd:6]))

CI is broken: AttributeError: module 'python_utils.types' has no attribute 'ParamSpec'

There seems to be a new issue relating to Python version in conda that is breaking the CI...

Traceback (most recent call last):
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/runpy.py", line 194, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/runpy.py", line 87, in _run_code
    exec(code, run_globals)
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/fasm2bels/__main__.py", line 20, in <module>
    from .fasm2bels import main
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/fasm2bels/fasm2bels.py", line 34, in <module>
    from rr_graph.capnp import graph2 as capnp_graph2
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/site-packages/rr_graph/capnp/graph2.py", line 23, in <module>
    from rr_graph import graph2
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/site-packages/rr_graph/graph2.py", line 30, in <module>
    from .utils import progressbar_utils
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/site-packages/rr_graph/utils/progressbar_utils.py", line 21, in <module>
    import progressbar as bar
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/site-packages/progressbar/__init__.py", line 5, in <module>
    from .bar import DataTransferBar
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/site-packages/progressbar/bar.py", line 13, in <module>
    from python_utils import types
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/site-packages/python_utils/__init__.py", line 1, in <module>
    from . import (
  File "/home/jgoeders/actions-runner/_work/bfasst/bfasst/third_party/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/lib/python3.8/site-packages/python_utils/decorators.py", line 8, in <module>
    P = types.ParamSpec('P')
AttributeError: module 'python_utils.types' has no attribute 'ParamSpec'

bfasst can't run without rapidwright

Since the physical netlist script imports from rapidwright, it's not currently possible to use run_design.py without having rapidwright installed. It would be nice to have a workaround to remove this dependency.

Use new rapidwright wrapper script to download device files

Rapidwright now has a convenient wrapper script that can be used to invoke it directly without having to worry about Java classpath. We can simply how we download the device files and remove the extra python script we have:

Xilinx/RapidWright#669 (comment)

This call and it's associate script could be replaced by the command in the issue linked above.

Python whitespace formatting in CI

The CI should include a test verifying that python files have been formatted properly with black.
The format target in the Makefile should check the bfasst directory (not just scripts)

run_design.py throws an error when the design is not within the designs folder

Physical netlist produces multiple GND instances.

There seems to be a bug in physical netlist generation that causes multiple GND instances:

python scripts/run_design.py designs/byu/tx xilinx_phys_netlist

Produces a netlist with:

  GND GND
       (.G(\<const0> ));
  GND GND_1
       (.G(GND_2));

install conformal locally

Add f4pga to available tools

Unit tests fail to clone github repo

Looks like there is something wrong with the servers' attempt to fetch the github repo.

Run actions/checkout@v3
Syncing repository: byuccl/bfasst
Getting Git version info
Copying '/home/jgoeders/.gitconfig' to '/home/jgoeders/actions-runner/_work/_temp/867c0907-9340-4817-9864-dbf05862306d/.gitconfig'
Temporarily overriding HOME='/home/jgoeders/actions-runner/_work/_temp/867c0907-9340-4817-9864-dbf05862306d' before making global git config changes
Adding repository directory to the temporary git global config as a safe directory
/usr/bin/git config --global --add safe.directory /home/jgoeders/actions-runner/_work/bfasst/bfasst
Deleting the contents of '/home/jgoeders/actions-runner/_work/bfasst/bfasst'
Initializing the repository
Disabling automatic garbage collection
Setting up auth
Fetching the repository
  /usr/bin/git -c protocol.version=2 fetch --no-tags --prune --progress --no-recurse-submodules --depth=1 origin +dacbd25c9d3d6dfd49c7c54fe4dce27b0d269625:refs/remotes/pull/245/merge
  remote: Duplicate header: "Authorization"
  Error: fatal: unable to access 'https://github.com/byuccl/bfasst/': The requested URL returned error: 400
  The process '/usr/bin/git' failed with exit code 128
  Waiting 18 seconds before trying again
  /usr/bin/git -c protocol.version=2 fetch --no-tags --prune --progress --no-recurse-submodules --depth=1 origin +dacbd25c9d3d6dfd49c7c54fe4dce27b0d269625:refs/remotes/pull/245/merge
  remote: Duplicate header: "Authorization"
  Error: fatal: unable to access 'https://github.com/byuccl/bfasst/': The requested URL returned error: 400
  The process '/usr/bin/git' failed with exit code 128
  Waiting [13](https://github.com/byuccl/bfasst/actions/runs/5550758485/jobs/10156901822?pr=245#step:3:14) seconds before trying again
  /usr/bin/git -c protocol.version=2 fetch --no-tags --prune --progress --no-recurse-submodules --depth=1 origin +dacbd25c9d3d6dfd49c7c54fe4dce27b0d269625:refs/remotes/pull/2[45](https://github.com/byuccl/bfasst/actions/runs/5550758485/jobs/10156901822?pr=245#step:3:50)/merge
  remote: Duplicate header: "Authorization"
  Error: fatal: unable to access 'https://github.com/byuccl/bfasst/': The requested URL returned error: 400
  Error: The process '/usr/bin/git' failed with exit code 128

This issue looks similar: actions/checkout#838

fasm2bels cache losing environment

Somehow the fasm2bels cache that we store in our local runners at ~/actions-runner/cache/fasm2bels is losing it's environment setup.

For example, the following job was run fine on CCL3: https://github.com/byuccl/bfasst/actions/runs/5716268634/job/15487425617, and you can see here that it's using it's cached version of fasm2bels. The action completes successfully.

From what I can tell, the very next job to run on CCL is this one: https://github.com/byuccl/bfasst/actions/runs/5716268947/job/15487428017. It also reports to be using the cached version of fasm2bels, except this time it runs into an error here stating FileNotFoundError: [Errno 2] No such file or directory: PosixPath('/home/jgoeders/actions-runner/cache/fasm2bels/env/conda/envs/f4pga_xc_fasm2bels/bin/python3').

When I SSH into the CCL3 machine and inspect ~/actions-runner/cache/fasm2bels, the env directory is now gone.

It looks like make dist-clean in fasm2bels (imported from here) could delete the env directory, but I don't see anywhere we are calling that.

Any ideas what could be deleting the fasm2bels environment files inside the cache?

Structural comparison doesn't validate net mapping

Currently the structural comparison only checks that all instances are mapped, and doesn't check that nets are mapped.

It looks like there are some unconnected nets we need to deal with before turning on this check.

Issue with physical netlist generation for byu/riscv_final

Line 786 in bfasst is breaking the weekly error injection CI. However, the same unit tests pass. The issue is most likely to be with designs that are part of the error_injection weekly test but not part of the physical_netlist unit test, since the error_injection test more comprehensively tests the designs in the byu design directory.
https://github.com/byuccl/bfasst/suites/14002997756/artifacts/781358036

Move rapidwright from installer to git clone

print_to_stdout inconsistent

It seems that run_design.py and run_experiment.py pass bool print_to_stdout to the flow_fcn(). Not all flow functions accept this parameter. Also, is this parameter needed? Maybe multi-threading could be edited to always print each thread to a different file and never to stdout (not sure why you would want all the threads printing to stdout). Otherwise, if the user does not want the results of the run then they should use >> to redirect stdout to a file.

Add job class with function pointer to its job and a list of the jobs it depends on
Change flows to create job objects to be executed.
Run experiment will run Flow.create() as preprocessing to build a list of jobs that needs done
Run experiment will cycle through the job list, running jobs with no dependencies as threads become available. When a thread finishes, run experiment removes that job from the remaining jobs' dependency lists (or set).
Run design will run jobs in the list consecutively (no need to worry about dependencies if job list is guaranteed to be in at least hierarchal order).
Run experiment/run design checks for BfasstException and prints errors/success messages accordingly

Physical netlist not outputting certain LUT routethrus

From the buttoncount design, a LUT routethru that is driving a CARRY4 is being missed and not added to the physical netlist.

	# TODO: After establishing mapping, verify equivalence
	# Basically make sure all outputs are mapped, and then everything is identical
	# Maybe this will already be guaranteed by the mapping algorithm? ...good to
	# double check.