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calvin's Projects

32-verilog-mini-projects icon 32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

academic-paper-tools icon academic-paper-tools

自制的学术论文工具汇总,欢迎大家将这些工具以源代码的方式放到这个项目里

algorithm-pattern icon algorithm-pattern

算法模板,最科学的刷题方式,最快速的刷题路径,你值得拥有~

android-app icon android-app

这是开源**社区的开源 Android 客户端项目,本项目已经迁移到码云 gitee.com 此处不再更新!

antlr4 icon antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

audio_noise_reduction_hardware_acceleration_system icon audio_noise_reduction_hardware_acceleration_system

基于PYNQ开发的人声音频降噪硬件加速系统,采用高通滤波器为主要算法,PYNQ-Z2开发板为上载硬件,采用PYNQ的软硬协同设计实现了实时的音频降噪功能,并且载入板卡后实现的效果,能够满足项目的开发需求。

autorccar icon autorccar

[hamuchiwa/AutoRCCar]项目的中文文档。每个代码文件都有同名markdwon文件来讲解。这是一个用 RC 小车、树莓派、Arduino和开源软件实现的小规模的自动驾驶项目。

awesome-python-cn icon awesome-python-cn

Python资源大全中文版,包括:Web框架、网络爬虫、模板引擎、数据库、数据可视化、图片处理等,由伯乐在线持续更新。

bnt icon bnt

Bayes Net Toolbox for Matlab

bsv_tutorial_cn icon bsv_tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。

cnn-fpga icon cnn-fpga

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

cnn-fpga-rtl icon cnn-fpga-rtl

The CNN architecture elements implemented with RTL approach in VHDL.

cnn_open icon cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

cocoapi icon cocoapi

COCO API - Dataset @ http://cocodataset.org/

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