Comments (5)
Do we need space for more than one track state on the CPU? Seems like we would have an outer loop over primaries and initialize the track from each primary/transport it one by one. The track initialization code (extend_from_primaries
, initialize_tracks
, extend_from_secondaries
) is all device-specific, so we'll different logic on the CPU anyway.
from celeritas.
The way I've been structuring things so far is to have a loop over thread IDs when adding an equivalent CPU "kernel", e.g.
https://github.com/paulromano/celeritas/blob/a611b0ba8adc23d56e8d086a6552153ed8678af9/src/physics/em/detail/KleinNishina.cc#L32-L33
This exposes some loop-level parallelism so that if we wanted to actually use CPU threads, it would be pretty straightforward. The alternative would be for the CPU kernels to omit that loop and instead have an outer loop over primaries, as you suggest. Either way, we'll need to have an outer loop for the case where # primaries > # tracks, so the question is really just on the inner loop do we want to allow more than one primary/track?
from celeritas.
One issue I've run into with trying to run the demo loop on CPU: right now, the problem consists of 15 primaries but we're only setting room in the state data for a single primary:
celeritas/app/demo-loop/LDemoRun.cc
Line 190 in b62d827
It looks like this is because
VGNavCollection
on the host only permits its size to be one, so increasing the above size just leads to precondition errors on the size of the navigation state. From what I can gather, the options to get around this are:
- Use
NavStatePool
on host as we currently do for device to allow multiple CPU "threads" - Extend the demo loop logic to account for the case where # primaries > # tracks (not yet implemented for GPU), and continue with a single primary on CPU
Any thoughts on the best path forward would be appreciated
from celeritas.
I think either approach would be fine, but single-threaded should be our initial goal and I will approve most expedients to get us there. :)
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Related Issues (20)
- Support Intel GPUs
- Add G4VG support for ALICE Geant4 geometry components HOT 5
- Build errors with GEANT4 11.2.0 HOT 2
- Add ORANGE construction of single units HOT 2
- Nonuniform Rayleigh scattering cross section grid in Geant4 11.2 HOT 4
- Update celer-g4 ROOT I/O
- Geant4 object model HOT 3
- Integrate Celeritas into CMSSW
- Integrate Celeritas into ATLAS
- Demonstrate ADIOS output on Frontier HOT 2
- Undefined references with CudaRDCUtils and vecgeom
- Collaborate with HEPiX for CPU/GPU performance and efficiency benchmarking
- Convert Geant4 geometry to ORANGE
- Implement single-track CPU for performance and improve integration HOT 6
- Implement CPU-only G4MagneticField wrapper
- Generate input documentation from app structs HOT 1
- Parameterized source distributions
- Better statistics from celer-sim
- Integrate Perfetto for optional CPU profiling HOT 3
- Make track IDs reproducible across runs
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