chipsalliance Goto Github PK

rocket-chip-blocks

RTL blocks compatible with the Rocket Chip Generator

rocket-chip-fpga-shells

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

rocket-pcblib

rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

silicon-notebooks

surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

sv-tests-results

Output of the sv-tests runs.

synlig

SystemVerilog support for Yosys

synlig-logs

systemc-compiler

Intel Compiler for SystemC

t1

tilelink

tools-cocotb-verilator-build

treadle

Chisel/Firrtl execution engine

tree-sitter-firrtl

FIRRTL grammar for tree-sitter

tsc

CHIPS Alliance Technical Steering Committee

uhdm

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

uhdm-integration-tests

uvm-verilator

veer-iss

veerwolf

FuseSoC-based SoC for SweRV EH1 and EL2

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

verible-actions-common

verible-formatter-action

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

verilator

Verilator open-source SystemVerilog simulator and lint system

vtr-xml-utils