Comments (3)
I have a related request. firtool doesn't release Windows executable before 1.45.0. But firtool 1.45.0 seems to generate system verilog by default (generate .sv when exeuting chisel3.emitVerilog). Can chisel support newer version of firtool?
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Chisel main branch is always supports the up to date version of firtool.
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As of Chisel 6.0.0 (and I hope to eventually backport similar support to 5.x and maybe even 3.6.x), Chisel now manages the version of firtool for you.
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Related Issues (20)
- emitVerilog generate empty output file with firtool option `split-verilog` HOT 2
- Nightly CI failed HOT 1
- SRAM blackbox substitution options needed in Chisel 6.2.0 HOT 4
- Layers are not emitted unless a block exists
- Switch and only maintain mill build
- Chisel6.0 multiplication Width Lint Errors HOT 1
- Bump Scalafmt HOT 1
- Printf to file
- mill format check failing in CI HOT 5
- Negative Width Gives Bad Error Message
- ProbeSpec and HarnessSpec tests fail HOT 5
- Pass Chisel information to firtool to generate debug information for the Tywaves project HOT 14
- Hard to obtain needed context to build IR for referencing results of `FirrtlMemory` HOT 3
- Connectable does not properly handle Views
- [Feature Request] expose outer class of `ChiselEnum#Type`
- provide an Chisel Native API for SystemVerilog bind HOT 2
- Provide suggestName to Queue(and other Chisel Library Moduels) HOT 1
- [Feature Request] Request MuxTLookup
- Support default connection via hasCustomConnect
- Mux or ProbeExpr of View doesn't work
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