Comments (4)
What is the error?
from chisel.
@mwachs5 wrote:
What is the error?
Edited it into the issue text at the bottom.
from chisel.
Basically I think this is a pitfall in chisel type system, in chisel it runtime modify the chisel type when a wire is connect to other wire.
Basically I think we need to think about embed all type information, here is the the Connectable semantic in FIRRTL spec and emit the connect IR, let firtool handle those errors. We should consider stopping detect these errors, make them a part of firrtl-spec and let a real compiler handle it.
from chisel.
This was added to detect a problematic case where bundles with Analog fields were assigned with a bulk connect for default values, and then later attempted to be overridden. In this instance, all non-Analog fields would be overridden, but without this error, Analog fields would be attached to both the default and the later "overriding" field.
The key incompatibility is last-connect-semantics with Analog signals doesn't make sense, so figuring out how bulk connects should work isn't likely going to have satisfactory semantics.
One idea I've been playing with is isolating last-connect-semantics with the :=
operator, but not with the connectable operators. So doing a :<= b; a:<= c
would be an error, but a :<= b; a.x := foo
would be ok.
from chisel.
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from chisel.