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0.0 1.0 0.0 7.45 MB

rv32i/rv32im/rv32imc for iCE40. Wishbone interface.

License: Apache License 2.0

Makefile 1.01% Verilog 58.04% C 16.86% Assembly 6.38% C++ 4.55% V 6.79% AGS Script 6.22% Coq 0.13% Shell 0.01%

midgetv's Introduction

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midgetv

midgetv is a RISC-V implementation written specifically for ice40* FPGAs. The base ISA is RV32I. Standard extensions Zicsr and Zifencei are always included. Standard extension C, M can be compiled in.

midgetv uses Wishbone b4 for interconnect.

To use midgetv

Include midgetv.v into your project, and instantiate m_midgetv_core. The program to run on the core is given by parameters prg00 through prg0F, usually generated by transforming a binary RISC-V program with the utility midgetv_bin2ebr.

More (rather unstructured) information is available here.

Semantic Versioning API specification

  1. Signal interface to module m_midgetv_core is part of the API.
  2. The coarse memory map of midgetv is part of the API.
  3. The way a binary file is mapped to localparam specifications by the utility midgetv_bin2ebr is part of the API.

midgetv's People

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