ctb-337/my-systemverilog-examples

A place to keep my synthesizable SystemVerilog code snippets and examples.

my-systemverilog-examples

A place to keep my synthesizable SystemVerilog code snippets and examples.

Table of Contents,

• BASIC CODE
  • COMBINATIONAL LOGIC
  • SEQUENTIAL LOGIC
• COMBINATIONAL LOGIC
  • ALUs
  • DATA OPERATORS
  • DECODERS & ENCODERS
  • MULTIPLEXERS & DEMULTIPLEXERS
• FPGA DEVELOPMENT BOARDS
  • BUTTONS
• SEQUENTIAL LOGIC
  • ARBITERS
  • COUNTERS
  • FINITE SATE MACHINES
  • MEMORY
  • REGISTERS
  • SHIFTERS
• SYSTEMS
  • MICROPROCESSORS
  • PIPELINES

Documentation and reference,

• iverilog is a free verilog simulator and synthesis tool
• GTKWave is a free waveform viewer
• SystemVerilog cheat sheet
• Xilinx Vivado cheat sheet for synthesis and burning an FPGA
• Digilent ARTY-S7 FPGA development board
• My Master's Thesis has an explanation of HDLs and how they fit into frameworks
• My Master's Thesis also has my design of a programable-8-bit-microprocessor

GitHub Webpage built with concourse ci

SCRIPT TO LAUNCH GTKWAVE

To make things easier when viewing a waveform, I wrote a script that will launch GTKWave with your saved *.gtkw file from Windows WSL, macOS or Linux (Whatever you use).

The script is launch-gtkwave.sh.

A QUICK NOTE ON SYNTHESIS

I declare my ports as follows because that's what the synthesis tools want. Who am I to argue,

    module NAME (
        input             a,     // Input A
        input       [7:0] b,     // Input B
        output reg  [3:0] y      // Output Y
    );

Also, I would stay away from asynchronous design. It can have problems when you synthesize to an FPGA.

    // DO THIS
    always @ (posedge clk) begin
        if (~reset) begin
            ...

    // NOT THIS
    always @ (posedge clk or negedge reset) begin

SYSTEMVERILOG EXAMPLES

All sections in alphabetical order. Each example uses iverilog to simulate and GTKWave to view the output. I also used Xilinx Vivado to synthesize and program these verilog examples on a Digilent ARTY-S7 FPGA development board. These examples also contain info I gathered from other sources.

BASIC CODE

• COMBINATIONAL LOGIC

  • and2

    2-input AND gate used in my programable-8-bit-microprocessor below.

  • and-gate

    A few different ways to model an AND gate.

  • nand4

    4-input NAND gate used in my programable-8-bit-microprocessor below.

  • nor2

    2-input NOR gate used in my programable-8-bit-microprocessor below.

  • not1

    NOT gate used in my programable-8-bit-microprocessor below.

  • or2

    2-input OR gate used in my programable-8-bit-microprocessor below.

  • xor2

    2-input XOR gate used in my programable-8-bit-microprocessor below.

• SEQUENTIAL LOGIC

  • d-flip-flop

    A positive edge d flip-flop with synchronous enable. Used in my jeff-74x377 below.

  • jk-flip-flop

    A positive edge jk flip-flop with synchronous clear. Used in my jeff-74x161 below.

COMBINATIONAL LOGIC

• ALUs

  • jeff-74x181

    4-bit alu (arithmetic logic unit) and function generator. Provides 16 binary logic operations and 16 arithmetic operations on two 4-bit words. Based on the 7400-series integrated circuits used in my programable-8-bit-microprocessor below.

• DATA OPERATORS

  • full-adder

    A 2-bit full-adder.

  • half-adder

    A 2-bit half-adder.

• DECODERS & ENCODERS

  • decoder-3-8

    Decoder - Three inputs decodes to 1 of 8 outputs (hot).

  • decoder-to-encoder

    Combining the decoder-3-8 to the encoder-8-3 to prove the input will equal the output.

  • encoder-8-3

    Encoder - Eights inputs (1 hot) encodes to output.

• MULTIPLEXERS & DEMULTIPLEXERS

  • demux-1x4

    Demultiplexer - One input, four outputs (using a case statement).

  • jeff-74x151

    8-line to 1-line data selector/multiplexer. Based on the 7400-series integrated circuits used in my programable-8-bit-microprocessor below.

  • jeff-74x157

    Quad 2-line to 1-line data selector/multiplexer, non-inverting outputs. Based on the 7400-series integrated circuits used in my programable-8-bit-microprocessor below.

  • mux-4x1

    Multiplexer - Four inputs, one output (using a case statement).

  • mux-to-demux

    Combining the mux-4x1 to the demux-1x4 to prove the input will equal the output (For the selected output).

FPGA DEVELOPMENT BOARDS

• BUTTONS

  • buttons

    A few different ways to use buttons on a FPGA development board.

SEQUENTIAL LOGIC

• ARBITERS

  • priority-arbiter

    A three level Priority Arbiter with asynchronous reset (Using if-then-else statements).

• COUNTERS

  • jeff-74x161

    Synchronous presettable 4-bit binary counter, asynchronous clear. Based on the 7400-series integrated circuits used in my programable-8-bit-microprocessor below.

• FINITE STATE MACHINES

  • pattern-recognition

    Recognize the pattern 00110 in a serial stream.

• MEMORY

  • simple-memory-using-1d-array

    A simple 16 Byte memory modeled using a 1D array.

• REGISTERS

  A bunch of flip-flops.

  • jeff-74x377

    8-bit register, clock enable. Based on the 7400-series integrated circuits used in my programable-8-bit-microprocessor below.

  • simple-8-bit-register

    A simple 8-bit register with synchronous load and clear.

• SHIFTERS

  • left-shift-register

    A 4-bit left shift register.

SYSTEMS

• MICROPROCESSORS

  • programable-8-bit-microprocessor

    A programable 8-bit microprocessor. Originally designed in VHDL for part of my Master's Thesis.

• PIPELINES

  • simple-pipeline

    A simple pipeline.