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Verilog 24.58% HTML 9.55% SystemVerilog 25.59% C 27.64% C++ 1.43% Standard ML 0.01% Scheme 0.01% Tcl 0.05% Assembly 3.90% Makefile 4.34% Shell 0.14% Logos 0.62% GDB 0.10% VHDL 2.04%

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