devbisme/skidl

SKiDL is a module that extends Python with the ability to design electronic circuits.

skidl

The SKiDL Python package lets you compactly describe the interconnection of electronic circuits and components. The resulting Python program performs electrical rules checking for common mistakes and outputs a netlist that serves as input to a PCB layout tool.

• Free software: MIT license
• Documentation: http://devbisme.github.io/skidl
• User Forum: https://github.com/devbisme/skidl/discussions

Features

• Has a powerful, flexible syntax (because it is Python).
• Permits compact descriptions of electronic circuits (think about not tracing signals through a multi-page schematic).
• Allows textual descriptions of electronic circuits (think about using diff and git for circuits).
• Performs electrical rules checking (ERC) for common mistakes (e.g., unconnected device I/O pins).
• Supports linear / hierarchical / mixed descriptions of electronic designs.
• Fosters design reuse (think about using PyPi and Github to distribute electronic designs).
• Makes possible the creation of smart circuit modules whose behavior / structure are changed parametrically (think about filters whose component values are automatically adjusted based on your desired cutoff frequency).
• Can work with any ECAD tool (only two methods are needed: one for reading the part libraries and another for outputing the correct netlist format).
• Can perform SPICE simulations (Python 3 only).
• Takes advantage of all the benefits of the Python ecosystem (because it is Python).

As a very simple example (see more in the blog), the SKiDL program below describes a two-input AND gate built from discrete transistors:

from skidl import *

# Create part templates.
q = Part("Device", "Q_PNP_CBE", dest=TEMPLATE)
r = Part("Device", "R", dest=TEMPLATE)

# Create nets.
gnd, vcc = Net("GND"), Net("VCC")
a, b, a_and_b = Net("A"), Net("B"), Net("A_AND_B")

# Instantiate parts.
gndt = Part("power", "GND")             # Ground terminal.
vcct = Part("power", "VCC")             # Power terminal.
q1, q2 = q(2)                           # Two transistors.
r1, r2, r3, r4, r5 = r(5, value="10K")  # Five 10K resistors.

# Make connections between parts.
a & r1 & q1["B C"] & r4 & q2["B C"] & a_and_b & r5 & gnd
b & r2 & q1["B"]
q1["C"] & r3 & gnd
vcc += q1["E"], q2["E"], vcct
gnd += gndt

generate_netlist()

And this is the output that can be fed to a program like KiCad's PCBNEW to create the physical PCB:

(export (version D)
  (design
    (source "/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/circuit.py")
    (date "05/11/2021 10:40 AM")
    (tool "SKiDL (1.0.0)"))
  (components
    (comp (ref #PWR1)
      (value GND)
      (footprint "No Footprint")
      (fields
        (field (name F0) #PWR)
        (field (name F1) GND))
      (libsource (lib power) (part GND))
      (sheetpath (names /top/16948080335112909674) (tstamps /top/16948080335112909674)))
    (comp (ref #PWR2)
      (value VCC)
      (footprint "No Footprint")
      (fields
        (field (name F0) #PWR)
        (field (name F1) VCC))
      (libsource (lib power) (part VCC))
      (sheetpath (names /top/10777333099431236833) (tstamps /top/10777333099431236833)))
    (comp (ref Q1)
      (value Q_PNP_CBE)
      (footprint "No Footprint")
      (fields
        (field (name F0) Q)
        (field (name F1) Q_PNP_CBE))
      (libsource (lib Device) (part Q_PNP_CBE))
      (sheetpath (names /top/5605641708446153824) (tstamps /top/5605641708446153824)))
    (comp (ref Q2)
      (value Q_PNP_CBE)
      (footprint "No Footprint")
      (fields
        (field (name F0) Q)
        (field (name F1) Q_PNP_CBE))
      (libsource (lib Device) (part Q_PNP_CBE))
      (sheetpath (names /top/3991298653620578089) (tstamps /top/3991298653620578089)))
    (comp (ref R1)
      (value 10K)
      (footprint "No Footprint")
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/17650585640079795295) (tstamps /top/17650585640079795295)))
    (comp (ref R2)
      (value 10K)
      (footprint "No Footprint")
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/11461493733231665754) (tstamps /top/11461493733231665754)))
    (comp (ref R3)
      (value 10K)
      (footprint "No Footprint")
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/1249286041592970488) (tstamps /top/1249286041592970488)))
    (comp (ref R4)
      (value 10K)
      (footprint "No Footprint")
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/7242640812520981502) (tstamps /top/7242640812520981502)))
    (comp (ref R5)
      (value 10K)
      (footprint "No Footprint")
      (fields
        (field (name F0) R)
        (field (name F1) R))
      (libsource (lib Device) (part R))
      (sheetpath (names /top/9932266607871614386) (tstamps /top/9932266607871614386))))
  (nets
    (net (code 1) (name A)
      (node (ref R1) (pin 1)))
    (net (code 2) (name A_AND_B)
      (node (ref Q2) (pin 1))
      (node (ref R5) (pin 1)))
    (net (code 3) (name B)
      (node (ref R2) (pin 1)))
    (net (code 4) (name GND)
      (node (ref #PWR1) (pin 1))
      (node (ref R3) (pin 2))
      (node (ref R5) (pin 2)))
    (net (code 5) (name N$1)
      (node (ref Q1) (pin 2))
      (node (ref R1) (pin 2))
      (node (ref R2) (pin 2)))
    (net (code 6) (name N$2)
      (node (ref Q1) (pin 1))
      (node (ref R3) (pin 1))
      (node (ref R4) (pin 1)))
    (net (code 7) (name N$3)
      (node (ref Q2) (pin 2))
      (node (ref R4) (pin 2)))
    (net (code 8) (name VCC)
      (node (ref #PWR2) (pin 1))
      (node (ref Q1) (pin 3))
      (node (ref Q2) (pin 3))))
)

skidl's Issues

PySpice optional

Am using Python2, but wanted to check Python 3. I see that PySpice is not optional for running SKiDL under Python3.

PySpice is big! The thing took 20 minutes to (fail to) install on my Ubuntu machine.

Since a minority of users will use PySpice, and it's quite big and (dare I say it) perhaps slightly brittle, it would be nice if it were optional.

Maybe friendlier if the PySpice import only happened if the PySpice function is called?

Factor code that parses and writes kicad file formats into a separate library

I think this is a generally useful component that many kicad scripting tools could use, no point in every tool rewriting or copy pasting this stuff.

skidl has trouble with the Digikey libraries due to encoding

I've installed the Digikey libraries from here on GitHub into Kicad. They aren't UTF-8 clean encoded and this gives skidl fits:

Python 3.6.8 (default, Jan 2 2019, 05:35:58)
[GCC 8.2.0] on linux
Type "help", "copyright", "credits" or "license" for more information.

from skidl import *
search('opamp')
lib_dir =
WARNING: Could not open directory ''
lib_dir = .
lib_dir = /mnt/tools/kicad/share/kicad/library
Traceback (most recent call last):h-Screen-Controllers.lib ...
File "", line 1, in
File "/home/sam/.python/3/lib/python3.6/site-packages/skidl/part_query.py", line 103, in search
tool) # Search for parts with that substring.
File "/home/sam/.python/3/lib/python3.6/site-packages/skidl/part_query.py", line 75, in search_libraries
tool=tool) # Open the library file.
File "/home/sam/.python/3/lib/python3.6/site-packages/skidl/SchLib.py", line 96, in init
load_func(filename, skidl.lib_search_paths[tool])
File "/home/sam/.python/3/lib/python3.6/site-packages/skidl/tools/kicad.py", line 121, in load_sch_lib
for line in f:
File "/home/sam/.python/3/lib/python3.6/codecs.py", line 321, in decode
(result, consumed) = self._buffer_decode(data, self.errors, final)
UnicodeDecodeError: 'utf-8' codec can't decode byte 0x99 in position 102: invalid start byte

When I use iconv to force encode them to UTF-8 skidl is happy.

Great work on skidl and your other tools! I share your aversion to schematic capture.

Composability of subcircuits

Let's say that I have a subcircuit for the main part of a buck converter, and I've parameterized it to accept an arbitrary inductor, diode, etc:

def buck_converter(
        nmos: Part,
        diode: Part,
        inductor: Part,
        cap_input: Part,
        cap_output: Part,
):
    @subcircuit
    def buck_impl(pwm: Net, v_in: Net, v_out: Net, gnd: Net):
        buck_inner_net = Net('buck_inner')

        nmos_inst = nmos.copy()
        nmos_inst['gate'] = pwm
        nmos_inst['drain'] = v_in
        nmos_inst['source'] = buck_inner_net

        inductor_inst = inductor.copy()
        inductor_inst['+'] = buck_inner_net
        inductor_inst['-'] = v_out

        diode_inst = diode.copy()
        diode_inst['-'] = buck_inner_net
        diode_inst['+'] = gnd

        cap_input_inst = cap_input.copy()
        cap_input_inst['+'] = v_in
        cap_input_inst['-'] = gnd
        cap_output_inst = cap_output.copy()
        cap_output_inst['+'] = v_in
        cap_output_inst['-'] = gnd

    return buck_impl

However, what if I want to replace the diode with synchronous rectification? What I'd like to be able to do is create another subcircuit that provides that functionality, and be able to pass it in as the diode parameter. As long as it has the same pin names, that should work.

However, I can't do that, as the Circuit interface is nothing like the Part interface, and I can't create a part with multiple components.

It seems to me that idea of a Circuit isn't a very nice abstraction. It serves as a bag of parts and nets, a duplicate of the data that is already stored in the part and net graph. Why can't that bag of parts and nets be built up as it is needed?

Turn on Travis CI testing on for this repo

This will then be free and automatic on each pull request. See: https://www.smartfile.com/blog/testing-python-with-travis-ci/

SKiDL and its dependence on symbols

Since SKiDL is a netlist generator without involving any schematics, why it depends on symbols? It seems more reliable to make connections direclty to the pins of the footprint. It is very annoying to search through kicad's library for an existing symbol or creating a new symbol, which is not actually necesary for generating the netlist. I know I can create a SKiDL symbol library but still...

Of course I realize that I'll lose information about the pin type (input, output etc.) and as a result - ERC checking.

IMO a good start is to provide a feature of creating a Part() without passing the part's library name, and then ERC will warn user that this part has no pin information and it cannot be checked.

Footprints not found pcbnew import

Made a simple start of a clock schematic with Skidl and generated a netlist without errors.
When I try to import the netlist into pcbnew (kicad 5.1.0) it gives errors saying it cannot find the footprints.

Error: Cannot add new symbol R1 due to missing footprint Resistor_SMD.pretty:R_0805_2012Metric.
Error: Cannot add new symbol Y1 due to missing footprint Crystal.pretty:Crystal_HC18-U_Vertical.
Error: Cannot add new symbol U1 due to missing footprint Package_SO.pretty:SOIC-14_3.9x8.7mm_P1.27mm.
Error: Cannot add new symbol R54 due to missing footprint Resistor_SMD.pretty:R_0805_2012Metric.
Error: Cannot add new symbol R2 due to missing footprint Resistor_SMD.pretty:R_0805_2012Metric.
Error: R1 footprint “R_0805_2012Metric” not found in any libraries in the footprint library table.
Error: Cannot add new symbol C1 due to missing footprint Capacitor_SMD.pretty:C_0805_2012Metric.
Error: C1 footprint “C_0805_2012Metric” not found in any libraries in the footprint library table.
Error: Y1 footprint “Crystal_HC18-U_Vertical” not found in any libraries in the footprint library table.
Error: U1 footprint “SOIC-14_3.9x8.7mm_P1.27mm” not found in any libraries in the footprint library table.
Error: R54 footprint “R_0805_2012Metric” not found in any libraries in the footprint library table.
Error: R2 footprint “R_0805_2012Metric” not found in any libraries in the footprint library table.

To test this I dropped a 7400 onto a schematic and exported its netlist. The footprint name is NOT (1) the same as I used in my skidl code, but pcbnew-import does not give any errors...?

So what am I doing wrong?

Here's the code:

from skidl import *

# libraries
logic74 = '74xx'
device = 'device'

# footprints
fpR = 'Resistor_SMD.pretty:R_0805_2012Metric'
fpC = 'Capacitor_SMD.pretty:C_0805_2012Metric'
fpXTAL = 'Crystal.pretty:Crystal_HC18-U_Vertical'
fpU14 = 'Package_SO.pretty:SOIC-14_3.9x8.7mm_P1.27mm'

# global nets
vcc = Net('VCC')
gnd = Net('GND')

xtal = Part(device, 'crystal', footprint=fpXTAL)
r1 = Part(device, 'R', value='470R', footprint=fpR)
r2 = Part(device, 'R', value='470R', footprint=fpR)
c1 = Part(device, 'C', value='100pF', footprint=fpC)
u1 = Part(logic74, '74LS00', footprint=fpU14)

u1[7] += gnd
u1[14] += vcc
u1[12] += vcc
u1[9] += vcc

xtal[1] += r1[1]
xtal[1] += u1[13]

r1[2] += c1[1]
r1[2] += u1[11]

r2[2] += c1[2]
r2[2] += u1[10]

xtal[2] += r2[1]
xtal[2] += u1[4]
xtal[2] += u1[5]
xtal[2] += u1[8]

clk14 = Net('Clk14')
r54 = Part(device, 'R', value='4K7', footprint=fpR)
r54.ref = 'R54'

r54[1] += vcc
r54[2] += clk14
r54[2] += u1[6]
#--------------------------------
generate_netlist()

Here is the example of the generated netlist 7400 part:

(comp (ref U1)
      (value 74LS00)
      (footprint Package_SO.pretty:SOIC-14_3.9x8.7mm_P1.27mm)
      (fields
        (field (name keywords) "TTL nand 2-input buffer")
        (field (name description) "quad 2-input NAND buffer"))
      (libsource (lib 74xx) (part 74LS00))
      (sheetpath (names /top/17017331776065520654) (tstamps /top/17017331776065520654)))

And here is the 7400 part generated from the schematic

(comp (ref U1)
      (value 74HC00)
      (footprint Package_SO:SOIC-14_3.9x8.7mm_P1.27mm)
      (datasheet http://www.ti.com/lit/gpn/sn74hc00)
      (libsource (lib 74xx) (part 74HC00) (description "quad 2-input NAND gate"))
      (sheetpath (names /) (tstamps /))
      (tstamp 5CCF1A6A)))

I assume it should be possible to import the skidl generated netlist into pcbnew, yes?

1. After typing in this whole story it occurred to me that the schematic netlist did not use the .pretty extension. I typed it in because of the skidl 'getting started' examples, but remove that and it works...

missing self parameter in Pin._is_attached method

Opening this as an issue because I'm not sure that the comment I just made here will show up anywhere useful otherwise :)

57c2cfd#commitcomment-21738990

RFC: easy_skidl - parsing component descriptions

I made a component description parser called Electro Grammar that currently works on SMD resistor, capacitors and LEDs (planning to expand this to other types of components as well).

I have been porting it to Python (still very much work-in-progress) and thought I would try and use it to make SKiDL a bit easier. Here is an example of what I have been playing around with today:

import skidl
from easy_skidl import *

r1 = resistor('1k 0603')
r2 = r1.copy()

c1 = capacitor('0.1uF 0805')

led1 = led('0805 red')

vin = skidl.Net('VIN')
gnd = skidl.Net('GND')

vin     += r1[1], r2[1]
r2[2]   += c1[1]
c1[2]   += gnd
led1[1] += r1[2]
led1[2] += gnd

more details in a notebook

Some things to note:

• those easy_skidl functions currently break the * comprehensions i.e. r1, r2 = resistor('1k') * 2 won't work, do you see a good way around that?
  Nevermind, I was confused about the TEMPLATE thing.
• I am planning to license Electro Grammar as AGPLv3 (is this an issue?)

Any comments on this at all are very much appreciated.

load_backup_lib should catch IOError when attempting to open backup lib file

Example stack trace:

  File "./deps/usr/local/lib/python2.7/site-packages/skidl/skidl.py", line 1345, in __init__
    part = lib[name].copy(1, TEMPLATE)
  File "./deps/usr/local/lib/python2.7/site-packages/skidl/skidl.py", line 827, in get_part_by_name
    parts = self.get_parts(name=name)
  File "./deps/usr/local/lib/python2.7/site-packages/skidl/skidl.py", line 805, in get_parts
    backup_lib = load_backup_lib()
  File "./deps/usr/local/lib/python2.7/site-packages/skidl/skidl.py", line 184, in func
    return f(*args, **kwargs)
  File "./deps/usr/local/lib/python2.7/site-packages/skidl/skidl.py", line 3605, in load_backup_lib
    exec(open(BACKUP_LIB_FILE_NAME).read())
IOError: [Errno 2] No such file or directory: 'myscriptname_lib_sklib.py'
make: *** [all] Error 1

The python file that it is trying to load doesn't and won't exist. Other exceptions are caught there, but not IOError.

Unexpectedly long results for search

Upon searching 'opamp', I get the following results, with a lot of warnings from unrelated parts.
What is this due to?
Can someone replicate this issue?
Also, it takes a lot of time to execute the search.

python
Python 2.7.12 (default, Nov 12 2018, 14:36:49)
[GCC 5.4.0 20160609] on linux2
Type "help", "copyright", "credits" or "license" for more information.

import skidl
from skidl import *
search('opamp')
WARNING: Could not open directory ''
WARNING: Non-identical pins with the same number (6) in symbol drawing BAT54ADW
WARNING: Non-identical pins with the same number (3) in symbol drawing BAT54ADW
WARNING: Non-identical pins with the same number (3) in symbol drawing BAV99
WARNING: Non-identical pins with the same number (6) in symbol drawing Rohm_UMP11N
WARNING: Non-identical pins with the same number (3) in symbol drawing Rohm_UMP11N
WARNING: Non-identical pins with the same number (2) in symbol drawing Rohm_UMN1N
WARNING: Non-identical pins with the same number (2) in symbol drawing Rohm_UMN1N
WARNING: Non-identical pins with the same number (2) in symbol drawing Rohm_UMN1N
WARNING: Non-identical pins with the same number (4) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (12) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3486N
WARNING: Non-identical pins with the same number (4) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (12) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3487DX
WARNING: Non-identical pins with the same number (4) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (8) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (12) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (16) in symbol drawing MC3487N
WARNING: Non-identical pins with the same number (1) in symbol drawing UA9637
WARNING: Non-identical pins with the same number (4) in symbol drawing UA9637
WARNING: Non-identical pins with the same number (1) in symbol drawing UA9638CD
WARNING: Non-identical pins with the same number (4) in symbol drawing UA9638CD
WARNING: Non-identical pins with the same number (1) in symbol drawing UA9638CP
WARNING: Non-identical pins with the same number (4) in symbol drawing UA9638CP
WARNING: Non-identical pins with the same number (AG19) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AH23) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AJ20) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AJ22) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AJ34) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AK13) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AK14) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AK23) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AK35) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AL22) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AM14) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AM22) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AN23) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AP20) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AP22) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AR23) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AM33) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AM34) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AM36) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AN31) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AN32) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AN34) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AN35) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AN36) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AP30) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AP32) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AP33) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AP35) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AP36) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AR30) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AR31) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AR33) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AR34) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AR36) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AT30) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AT31) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AT32) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AT33) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AT34) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AT35) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (AK34) in symbol drawing P4080-BGA1295
WARNING: Non-identical pins with the same number (29) in symbol drawing PIC16F871-IPT
WARNING: Non-identical pins with the same number (1) in symbol drawing 74LVC2G53
WARNING: Non-identical pins with the same number (2) in symbol drawing 74LVC2G53
WARNING: Non-identical pins with the same number (5) in symbol drawing 74LVC2G53
WARNING: Non-identical pins with the same number (6) in symbol drawing 74LVC2G53
WARNING: Non-identical pins with the same number (7) in symbol drawing 74LVC2G53
WARNING: Non-identical pins with the same number (1) in symbol drawing 74LVC1G3157
WARNING: Non-identical pins with the same number (2) in symbol drawing 74LVC1G3157
WARNING: Non-identical pins with the same number (5) in symbol drawing 74LVC1G3157
WARNING: Non-identical pins with the same number (6) in symbol drawing 74LVC1G3157
Searching Analog_Switch.lib ..WARNING: Non-identical pins with the same number (1) in symbol drawing IRF6802SD
WARNING: Non-identical pins with the same number (1) in symbol drawing 74LS78
WARNING: Non-identical pins with the same number (5) in symbol drawing 74LS78
WARNING: Non-identical pins with the same number (7) in symbol drawing EABC80
Amplifier_Audio.lib: OPA1622 (High-Fidelity, Bipolar-Input, Audio Operational Amplifier, VSON-10)
Amplifier_Audio.lib: LM386 (Low Voltage Audio Power Amplifier, DIP-8/SOIC-8/SSOP-8)
Amplifier_Difference.lib: LM733CH (Single Differential Amplifier, TO-5-10)
Amplifier_Difference.lib: LM733CN (Single Differential Amplifier, DIP-14)
Amplifier_Instrumentation.lib: INA327 (Precision, Rail-to-Rail I/O Instrumentation Amplifier, MSOP-10 package)
Amplifier_Instrumentation.lib: INA128 (Precision, Low Power Instrumentation Amplifier G = 1 + 49.4kOhm/Rg, DIP-8/SOIC-8)
Amplifier_Instrumentation.lib: INA326 (Precision, Rail-to-Rail I/O Instrumentation Amplifier, MSOP-8 package)
Amplifier_Operational.lib: AD8603 (Zero-Drift, Precision, Low-Noise, Rail-to-Rail Output, 36-V Operational Amplifier, TSOT-23-5)
Amplifier_Operational.lib: NE5534 (Single Low-Noise Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: OP179GS (Single Rail-to-Rail High Output Current Operational Amplifiers, SOIC-8)
Amplifier_Operational.lib: CA3130 (4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output, DIP-8/SOIC-8)
Amplifier_Operational.lib: THS4631DDA (Single High-voltage, High Slew Rate, Wideband, FET-input Operational Amplifier, MSOP-8)
Amplifier_Operational.lib: LMV321 (Single Low-Noise, Low Quiescent Current, Precision Operational Amplifier e-trim Series, SC-70-5)
Amplifier_Operational.lib: ADA4530-1 (Femtoampere Input Bias Current Electrometer Amplifier, SOIC-8)
Amplifier_Operational.lib: MCP603-xCH (Single 2.7V to 6.0V Single Supply CMOS Op Amps, with Chip Select, SOT-23-6)
Amplifier_Operational.lib: MCP601-xP (Rail-to-Rail Input/Output Operational Amplifier, PDIP-8)
Amplifier_Operational.lib: LTC6082xDHC (Precision Quad CMOS Rail-to-Rail Input/Output Amplifiers, DFN-16)
Amplifier_Operational.lib: LTC6362xMS8 (Precision, Low Power, Rail-to-Rail Input/Output, Differential Op Amp/SAR ADC Driver, DFN-8)
Amplifier_Operational.lib: L272M (Dual Power Operation Amplifier, DIP-8)
Amplifier_Operational.lib: MAX4238AUT (Ultra-Low Offset/Drift, Low-Noise, Precision Amplifiers, SOT-23-6)
Amplifier_Operational.lib: LM321 (Low Power Single Operational Amplifier, SOT-23-5)
Amplifier_Operational.lib: LTC6082xGN (Quad Single-Supply, Rail-to-Rail Operational Amplifier, MicroAmplifier Series, SSOP-16)
Amplifier_Operational.lib: NCS325 (Single operational amplifier, 50uV Offset, 0.25uV/C, 35uA Zero-Drift, SOT-23-5)
Amplifier_Operational.lib: LTC6081xDD (Precision Dual CMOS Rail-to-Rail Input/Output Amplifiers, DFN-10)
Amplifier_Operational.lib: LM4250 (Programmable Operational Amplifier, DIP-8/SOIC-8)
Amplifier_Operational.lib: LMH6551MM (Differential, High-Speed, Op Amp, VSSOP-8)
Amplifier_Operational.lib: OPA2333xxDRB (Dual 1.8V, microPower, CMOS Operational Amplifiers, Zero-Drift Series, SON-8)
Amplifier_Operational.lib: TSV912IQ2T (Dual rail-to-rail input/output 8 MHz operational amplifiers, DFN-8)
Amplifier_Operational.lib: LM318M (Operational Amplifier, DIP-8)
Amplifier_Operational.lib: OPA2695xD (Dual, Ultra-Wideband, Current-Feedback Operational Amplifier with Disable, SOIC-8)
Amplifier_Operational.lib: THS3491xDDA (900-MHz, 500-mA High-Power Output Current Feedback Operational Amplifier, SOIC-8)
Amplifier_Operational.lib: LMV601 (1MHz, Low-Power, General-Purpose, 2.7V Operational Amplifiers, SC-70-6)
Amplifier_Operational.lib: LTC1152 (Rail-to-Rail Input, Rail-to-Rail Output, Zero-Drift Op Amp, DIP-8, SOIC-8)
Amplifier_Operational.lib: OP279 (Dual Rail-to-Rail High Output Current Operational Amplifiers, SOIC-8/TSSOP-8)
Amplifier_Operational.lib: NCS2325D (Dual operational amplifier, 50uV Offset, 0.25uV/C, 35uA Zero-Drift, SOIC-8)
Amplifier_Operational.lib: OPA890xD (Single Low-Power, Wideband, Voltage-Feedback Operational Amplifier with Disable, SO-8)
Amplifier_Operational.lib: LTC1151CN8 (Dual ±15V, Zero-Drift, Operational Amplifier, DIP-8)
Amplifier_Operational.lib: OPA2691-14 (Dual Wideband, Current-Feedback Operational Amplifier With Disable, SOIC-14)
Amplifier_Operational.lib: TSV524xIQ4T (Quad CMOS Rail-to-Rail Input/Output Amplifier, 1.15MHz GBP, QFN-16)
Amplifier_Operational.lib: ADA4898-2 (Dual High Voltage, Low Noise, Low Distortion, Unity-Gain Stable, High Speed Op Amp, SOIC-8-1EP)
Amplifier_Operational.lib: LMH6551MA (Differential, High-Speed, Op Amp, SOIC-8)
Amplifier_Operational.lib: OPA330xxYFF (50μV V OS, 0.25μV/°C, 35μA CMOS OPERATIONAL AMPLIFIERS, Zerø-Drift Series, DSBGA)
Amplifier_Operational.lib: LM318J (Operational Amplifier, DIP-14)
Amplifier_Operational.lib: LTC1151CSW (Dual ±15V, Zero-Drift, Operational Amplifier, SOIC-16W)
Amplifier_Operational.lib: ADA4898-1YRDZ (High Voltage, Low Noise, Low Distortion, Unity-Gain Stable, High Speed Op Amp, SOIC-8)
Amplifier_Operational.lib: MCP6L91RT-EMS (10 MHz, 850 µA Op Amps, MSOP-8)
Amplifier_Operational.lib: MCP6002-xMC (1MHz, Low-Power Op Amp, DFN-8)
Amplifier_Operational.lib: LM741 (Single JFET-Input Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: OP179GRT (Single Rail-to-Rail High Output Current Operational Amplifiers, SOT-23-5)
Amplifier_Operational.lib: OPA355NA (200MHz, CMOS, Operational amplifier, with shutdown, SOT-23-6)
Amplifier_Operational.lib: OP249GS (Precision JFET, High Speed, Dual Operational Amplifier, SOIC-8)
Amplifier_Operational.lib: L272 (Dual Power Operation Amplifier, DIP-16)
Amplifier_Operational.lib: OPA2376xxYZD (Dual Low-Noise, Low Quiescent Current, Precision Operational Amplifier e-trim Series, DSBGA-8)
Amplifier_Operational.lib: LMH6611 (Single Supply, 345 MHz, Rail-to-Rail Output, Amplifier, TSOT-23-6)
Amplifier_Operational.lib: MCP6L91RT-EOT (Single rail-to-rail input/output 8 MHz operational amplifiers, SOT-23-5)
Amplifier_Operational.lib: NCS4325 (Quad operational amplifier, 50uV Offset, 0.25uV/C, 35uA Zero-Drift, SOIC-14)
Amplifier_Operational.lib: LM2904 (Dual rail-to-rail input/output 8 MHz operational amplifiers, MiniSO-8)
Amplifier_Operational.lib: OPA1641 (JFET input, ultralow distortion, low-noise operational amplifier, SOIC-8/VSSOP-8)
Amplifier_Operational.lib: OP07 (Single SoundPlus High Performance Audio Operational Amplifiers, DIP-8/SOIC-8)
Amplifier_Operational.lib: ADA4841-1YRJ (Low Power, Low Noise and Distorsion, Rail-to-Rail Output Amplifier, SOT-23-6)
Amplifier_Operational.lib: OPA890xDBV (Single Low-Power, Wideband, Voltage-Feedback Operational Amplifier with Disable, SOT-23-6)
Amplifier_Operational.lib: LM675 (Power Operational Amplifier, TO-220-5)
Amplifier_Operational.lib: NCS2325DM (Dual operational amplifier, 50uV Offset, 0.25uV/C, 35uA Zero-Drift, MSOP-8)
Amplifier_Operational.lib: OPA2325 (Precision, 10-MHz, Low-Noise, Low-Power, RRIO, CMOS Operational Amplifier, SOIC-8)
Amplifier_Operational.lib: MAX4238ASA (Ultra-Low Offset/Drift, Low-Noise, Precision Amplifiers, SOIC-8)
Amplifier_Operational.lib: OPA2695xRGT (Dual, Ultra-Wideband, Current-Feedback Operational Amplifier with Disable, QFN-16)
Amplifier_Operational.lib: ADA4807-2ACP (Dual Rail-to-Rail Input/Output Amplifiers, with disable, SC-70-6/SOT-23-6)
Amplifier_Operational.lib: ADA4870ARRZ (High Speed, High Voltage, 1A Output Drive Amplifier, PSOP-20)
Amplifier_Operational.lib: LM6361 (Single High Speed Operational Amplifier, DIP-8/SOIC-8)
Amplifier_Operational.lib: MCP601-xST (Single 2.7V to 6.0V Single Supply CMOS Op Amps, TSSOP-8)
Amplifier_Operational.lib: LM2902 (Quad Rail-to-rail, 20 MHz GBP, operational amplifiers, SOIC-14/TSSOP-14)
Amplifier_Operational.lib: MCP6L91T-EOT (Single rail-to-rail input/output 8 MHz operational amplifiers, SOT-23-5)
Amplifier_Operational.lib: ADA4807-1 (Single Rail-to-Rail Input/Output Amplifiers, with disable, SC-70-6/SOT-23-6)
Amplifier_Operational.lib: MCP603-xP (Single 2.7V to 6.0V Single Supply CMOS Op Amps, with Chip Select, TSSOP-8)
Amplifier_Operational.lib: OPA333xxD (Single rail-to-rail input/output 8 MHz operational amplifiers, SOIC-8)
Amplifier_Operational.lib: L272D (Dual Power Operation Amplifier, SOIC-16)
Amplifier_Operational.lib: LTC6362xDD (Precision, Low Power, Rail-to-Rail Input/Output, Differential Op Amp/SAR ADC Driver, DFN-8)
Amplifier_Video.lib: AD813 (Single Supply, Low Power, Triple Video Amplifier, DIP-14/SOIC-14)
Device.lib: Opamp_Dual_Generic (Dual operational amplifier)
Device.lib: Opamp_Quad_Generic (Quad operational amplifier)
Power_Management.lib: TSM103W (Dual Operational Amplifier and 2.5V 0.4% Voltage Reference, SOIC-8)
Power_Management.lib: TSM102 (Dual Operational Amplifier and Dual Comparator and 0.4% Voltage Reference, SOIC-16)
Simulation_SPICE.lib: OPAMP (Operational amplifier, single, node sequence=1:+ 2:- 3:OUT 4:V+ 5:V-)
pspice.lib: OPAMP (OPAmp symbol for simulation only)

XML file generation

SKiDL should generate an XML file in the same manner that EESCHEMA does. This can be used for generating BOMs.

visualizer/viewer

It would be awesome if you could build a graphical schematic from the netlist file (or python script). you could integrate it to letex for viewing or have the flexibility of switching from and to a graphical schematic digram.

PySpice Part('K') Coupled inductors params

https://github.com/xesscorp/skidl/blob/78fdc0a331e1be4cd127d5a8ad33ce27c4505ead/skidl/libs/pyspice_sklib.py#L389

for me work

    pyspice={
            'name': 'K',
            'kw': {
                'inductor1':'inductor1', 'inductor2':'inductor2', 'coupling_factor':'coupling_factor',
            },
            'add': add_part_to_circuit,
        }

Inductor1 and Inductor2 should be the .ref of the part in SPICE netlist.

Regex on Part pins causes confusion

When referring to pins by name, the regex interpretation causes confusion. I find it much clearer to refer to pins by name, rather than number. Is there a way of getting an exact match?

For example trying this part:

from skidl import *

j1 = Part('conn', 'USB_OTG')
print j1
print
print j1['D+']

As you can see, "D+" actually matches 5 pins!

 USB_OTG (): USB mini/micro connector
    Pin J1/1/VBUS/POWER-IN
    Pin J1/2/D-/PASSIVE
    Pin J1/3/D+/PASSIVE
    Pin J1/4/ID/PASSIVE
    Pin J1/5/GND/POWER-IN
    Pin J1/6/Shield/PASSIVE

[Pin J1/2/D-/PASSIVE, Pin J1/3/D+/PASSIVE, Pin J1/4/ID/PASSIVE, Pin J1/5/GND/POWER-IN, Pin J1/6/Shield/PASSIVE]

Yeah, I know I can write:

j1['^D\+$']

But that loses a lot of the clarity that I'm hoping to get from using SKiDL

zyc suggestions

You've created another great tool - zyc is very, very convenient.

A couple of suggestions:
-- I use a dark theme and the search results are invisible unless I highlight them. To get around that I use "env GTK_THEME=Adwaita:light zyc" but either handling light and dark themes or allowing us to choose font colors would be nice.
-- I use Liberation Mono with a fairly large font size and the various buttons (esp the search button) clip their text - automatically resizing the buttons to account for different text sizes would also be nice. The "Searching..." popup text also clips.

I can provide a screenshot if that would help.

Spelling error in default examples for Kicad 5

In Kicad 5, Part('device') has to be Part('Device.lib').

RFC: overloading the >> operator for connections

While working on #25 I had some thoughts that could help make circuits more readable. It may be possible to overload the >> operator in a way that turns

vin       += r1[1], r2[1]
r2[2]     += c1[1]
c1[2]     += gnd
led1['a'] += r1[2]
led1['k'] += gnd

into

vin >> r2 >> c1 >> gnd
vin >> r1 >> led1['a']; led1['k'] >> gnd 

Some things to note:

• It needs to accept Net, Pin and Part (edit: and Bus!)
• Giving a Part will assume it "flows" into pin 1 and out pin 2 so these are equivalent:

vin >> r1[1]; r1[2] >> gnd
vin >> r1 >> gnd

There may some blocker for making this possible in the way Python works, haven't investigated fully, but for now it would just be good to know if others agree that it would be desirable.

I don't think overloading <<, allowing connections in the other direction, would be desirable as it would make for more confusing circuit descriptions.

Lazy part parameters.

One of the tasks I hate most is switching out parts for a near replacement. Replacing a handful of like components to tweak a parameter on a reused module. These are all tasks that a program can do for us with less errors. I have had to get boards respun because a copied schematic page had too small of components and we missed changing a few of them, or a copy paste error made all the resistors 10K when we only wanted to change the size. This is largely an issue with graphical schematics, and can be clearly worked around, but some lower level support here could ease this task.

Let's start with the documentations resistor divider example, clearly contrived in this case as it's only two components!

@SubCircuit
def vdiv(inp, outp):
    """Divide inp voltage by 3 and place it on outp net."""
    rup = Part('device', 'R', value='1K', footprint='Resistors_SMD:R_0805')
    rlo = Part('device', 'R', value='500', footprint='Resistors_SMD:R_0805')
    rup[1,2] += inp, outp
    rlo[1,2] += outp, gnd

This implements two simple components but sets the footprint, so this sub circuit is not completely reusable across projects. If I go to use this subcircuit in a different design that is using R_0402 footprints then I have to go edit this module or monkey patch the the resistors parameters later. It also is missing information like the tolerance, temperature coefficient, power dissipation, and many more that might be required for a successful implementation.

There are many ways to address this, like passing in a footprint to the function. I want to make decisions when it is the proper time to make these decisions.

This issue is to propose a processing step that builds up the components that lack required attributes until they are fully defined for the BOM.
This step would:

• Process lazily bound or unset attributes.
• Compute optimal sizes
• Highlight conflicting requirements.
• Optionally choose from components that you commonly use and have on hand.
  • Your nearly full reel of 10KΩ 1% 0603 resistors, but switching all new purchases to 0402.

Let's take that resistor divider and add some of these concepts.

from skidl.footprints import R_0402, R_0805  
# Assuming we have footprint classes that have additional information.
`R_0402 < R_0805` would evaluate to `True`

@SubCircuit
def vdiv(inp, outp):
    """Divide inp voltage by 3 and place it on outp net.
         Make it easy to change out the lower resistor for tuning"""
    rup = Part('device', 'R', value='1K', tol='1%, temp_co='<=150 ppm')
    rlo = Part('device', 'R', value='500', tol='1%', hand_solderable=True)
    rup[1,2] += inp, outp
    rlo[1,2] += outp, gnd
# Snip

resolve_schematic(min_footprint=R_0402, hand_solderable=R_0805, ...)  # Like the linker step in compiling.
generate_netlist(tool='kicad', ...)
generate_bom(...)

Here we have the parts with additional parameters I care about, nothing more. The resolve step then sets things that matter when the design is going on to the next step, and we care about it.

Actions needed to implement this concept.

• Add a rule to the ERC that requires a valid footprint.
• Add a step to resolve lazy bound parameters.
  • Add _resolve function to Part class and run through a list of resolvable actions.
  • Call all functions with prefix _resolve_*
• Add a step to output BOM related parameters (tolerance, temp co, footprint, value, and etc...).
  • Propose: JSON list of dictionaries
• Determine better way to specify preferred lazy parameters.
  • Minimum pin pitch
  • Minimum square area
  • Would like to avoid explicit ordered lists.
• Resolve issue #7 on normalizing footprint names based on tools.

Example _resolve_footprint function.

def _resolve_footprint(self, **cfg):
    if self.footprint is not None:
        return
    if self.hand_solderable:
        if 'hand_solderable' in cfg:
            self.footprint = cfg['hand_solderable']
        else:
            self.footprint global_default_cfg['hand_solderable']
    else:
        self.footprint = max(global_default_cfg['min_footprint'], cfg['min_footprint'])

Invalid escape sequence in part_query.py

/home/travis/build/xesscorp/skidl/skidl/part_query.py:329
  /home/travis/build/xesscorp/skidl/skidl/part_query.py:329: DeprecationWarning: invalid escape sequence \(
    set(re.findall("\(\s*pad\s+([^\s)]+)", " ".join(module_text)))

Bussed part pins syntax broken for bus length > 9

Hello,

Loving skidl, but having an issue with creating a 16 bit wide bus.

I have a microcontroller with a series of pins named FMC_D0 through FMC_D15.

The following returns a list of length 22:

mcu['FMC_D[0:15]']

The pins 10-15 are being returned twice, and not in the proper order.

The following returns the same as above:

mcu['FMC_D[0:9]']

Modifying it to the following only returns only two exact pins:

mcu['FMC_D[0:9]\W']

Am I doing this incorrectly?

I can paste the .lib file if needed. I can confirm now that there is only one of each pin in the file. There isn't more than one pin with FMC_D11 in the name for example.

Export to Eeschema Schematic

Would it be possible for skidl to export into Eeschema?

The use case, is that it would be really powerful to generate a circuit description in Python code using skdl and then visualize it in Eeschema.

Adding placement and/or routing functionality

I would like to do some brainstorming about the possibility of adding placement and / or routing hints.

Problem

After generating a netlist and importing it into pcbnew you are left with the still tedious task of placing the footprints, drawing the traces and general layout.
But I think functionality can be added to include at least placement hints along with the generated netlist as in many cases you already know in loose terms where a particular part should be.

Possible approaches

Include information about part placement in the netlist

For example: (place parts right edge at 20 mil from the origin, center 100 mil from the origin)

{"right": "20mil", "y": "100mil"}

Maybe just add it into the value field, then use a python script from pcbnew to parse the placement data if it contains json with the relevant fields.

Generate kicad_pcb file from the start

Since the file formats of .net and .kicad_pcb are fairly similar it might be more convenient to go ahead and generate a kicad_pcb file that already has the parts placed.
Any tips where to start in regards to existing skidl code?
It might be useful to come up with an intelligent approach where an existing file isn't overwritten but "patched" with the new position.

UnicodeDecodeError when generating netlist

I am just trying to replicate the generation of the Arduino netlist using skidl.

I am using the last version of both KiCAD and skidl and I get this error when executing the skidl script.

Traceback (most recent call last):
File "arduino_skidl.py", line 678, in
generate_netlist()
File "/usr/local/lib/python2.7/dist-packages/skidl/Circuit.py", line 515, in generate_netlist
netlist = gen_func(**kwargs) # Pass any remaining arguments.
File "/usr/local/lib/python2.7/dist-packages/skidl/tools/kicad.py", line 458, in gen_netlist
netlist += '\n' + p.generate_netlist_component(KICAD)
File "/usr/local/lib/python2.7/dist-packages/skidl/Part.py", line 698, in generate_netlist_component
return gen_func()
File "/usr/local/lib/python2.7/dist-packages/skidl/tools/kicad.py", line 500, in gen_netlist_comp
fld_value = add_quotes(self.dict[fld_name])
File "/usr/local/lib/python2.7/dist-packages/skidl/utilities.py", line 278, in add_quotes
return '"' + s + '"'
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 26: ordinal not in range(128)

Improving performance

I love skidl, it is just what I need for reducing tediousness of digital designs. However, I find performance to be slow. If I have a python script that generatets a netlist, it takes about 15 seconds for it to load libraries and get through the skidl builders. I feel like it likely the parse time of libraries, but the profiling output wasn't super obvious.

Does anyone have any workaround for this issue (caching, etc). I find I want to iterate quickly as I incrementally build up a circuit. Maybe some caching would help? I'm going to play with mini_reset(), but I tend to have a workflow where I reload() a class that contains a circuit so I might lose the instance in my current scheme.

Thanks for the great software!

Add footprint class to normalize footprint representations.

Currently footprint names are hard coded in the programs.

The footprints should be converted into a class that is then resolved based upon the tool being output into.
Optionally we could also output the source used to make the footprint for the layout tool.

R_0402_info = {
    KICAD: {'footprint': 'Resistors_SMD:R_0805'},
    PCB_GEDA: {'footprint': "0805",
                           'footprint_source': "Insert M4 footprint source code here.",
    },
}

R_0402 = Footprint(R_0402_info)

I seem to recall that there was a standard for industry standard footprints.
http://www.ipc.org/ContentPage.aspx?pageid=Land-Pattern-Calculator
Not sure of it's use but they claim support for kicad.

ORM-like definition of new parts

Description

At the moment, I have to go into the KiCad library editor to create a new part. The net connections and net list are generated using skidl, but skidl is still utterly dependent on existing part libraries generated using KiCad.

I would like to see a 'model' or library that creates the part itself in python. We see similar models when we look as sqlalchemy classes which define and correspond to tables. In sqlalchemy, most users will create a models.py file which will entirely contain the SQL structure and my proposal is to implement a similar feature in skidl.

Motivation

This is OK, but it would be much more pythonic - and readable! - to create models using python syntax and use that to instantiate my part. Schematic part creation is great for those who have an existing library, but to use skidl for the workflow, it makes sense to have a 'from scratch' skidl option.

Current Part Generation

Using the example 'pic10f220-i/ot' from the documentation. The PIC10 has to be created using the schematic editor and skidl has to be configured to find that library and import it. The part definition is then entirely based on the KiCad part definition.

import skidl
pic10 = Part(lib='microchip_pic10mcu', name='pic10f220-i/ot')

Proposed Part Generation

The proposed ORM-like structure would likely consist of a custom library-like file and then the use-case (though it wouldn't have to be separated).

my_custom_parts.py

import skidl

class Pic10(BasePart):
    name = 'pic10f220-i/ot'
    pins = [
        Pin(num=1, name='ICSPDAT/AN0/GP0', funct=skidl.Pin.BIDIRECTIONAL),
        Pin(num=2, name='VSS', funct=skidl.Pin.POWER-IN),
        Pin(num=3, name='ICSPCLK/AN1/GP1', funct=skidl.Pin.BIDIRECTIONAL),
        Pin(num=4, name='T0CKI/FOSC4/GP2', funct=skidl.Pin.BIDIRECTIONAL),
        Pin(num=5, name='VDD', funct=skidl.Pin.POWER-IN),
        Pin(num=6, name='Vpp/~MCLR~/GP3', funct=skidl.Pin.INPUT)
    ]
    # more stuff could be added, but wouldn't have to be - manufacturer, part number, etc

my_circuit.py

pic10 = Part(basepart=Pic10)

Additional Features

Assuming that the proposed feature is implemented, it would also be nice to have a 'lib_to_skidl.py' script similar in functionality to the existing 'netlist_to_skidl.py' that exists now.

Units: Cannot use the same alias for multiple pins

Now this may be me not knowing python :-)

This code

part = Part('74xx', '74LS32')
part.make_unit('A', 1, 2, 3)
part.A.set_pin_alias('1A', 1)

gives this error

ERROR: Cannot use the same alias for multiple pins.

Looking at the Part.py source I think somehow my pin '1' is interpreted as a list of pins.
Not sure why.

Also I was surprised that the units were not already there, I can see them in the KiCad symbol editor? I call set_default_tool(KICAD) to make sure those are used....?

KiCad Connection Problems With New Installation

Hi,

I just installed skidl and I can't get the example in the README to work.

from skidl import *

# Create input & output voltages and ground reference.
vin, vout, gnd = Net('VI'), Net('VO'), Net('GND')

# Create two resistors.
r1, r2 = 2 * Part('device', 'R', TEMPLATE, footprint='Resistor_SMD.pretty:R_0805_2012Metric')

....
....

generate_netlist()

I'm on Ubuntu 18.04. The errors are KiCad related but I'm not familiar with the software (I did install it) so I'm not completely sure what's wrong. Here's my env variable with the path from KiCad's preferences: export KICAD_SYMBOL_DIR="/usr/share/kicad/library" and the stack trace.

ERROR: Can't open file: device.

WARNING: Could not load KiCad schematic library "device", falling back to backup library.
Traceback (most recent call last):
  File "/home/gordon/anaconda3/lib/python3.6/site-packages/skidl/tools/kicad.py", line 69, in _load_sch_lib_
    f, _ = find_and_open_file(filename, lib_search_paths_, lib_suffixes[KICAD])
  File "/home/gordon/anaconda3/lib/python3.6/site-packages/skidl/utilities.py", line 263, in find_and_open_file
    raise FileNotFoundError
FileNotFoundError

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "test.py", line 7, in <module>
    r1, r2 = 2 * Part('device', 'R', TEMPLATE, footprint='Resistor_SMD.pretty:R_0805_2012Metric')
  File "/home/gordon/anaconda3/lib/python3.6/site-packages/skidl/Part.py", line 139, in __init__
    raise e
  File "/home/gordon/anaconda3/lib/python3.6/site-packages/skidl/Part.py", line 131, in __init__
    lib = SchLib(filename=libname, tool=tool)
  File "/home/gordon/anaconda3/lib/python3.6/site-packages/skidl/SchLib.py", line 96, in __init__
    load_func(filename, skidl.lib_search_paths[tool])
  File "/home/gordon/anaconda3/lib/python3.6/site-packages/skidl/tools/kicad.py", line 73, in _load_sch_lib_
    filename, str(e)))
Exception: Unable to open KiCad Schematic Library File device ()

Add ability to use Eagle part libraries.

skidl.libs.* not accessible or searchable

I can't get SKiDL to search skdil.libs.

I'm quite sure adding a Part with the lines below worked at some point, but can't seem to reproduce it!

In [1]:  from skidl import *
In [2]:  AD620 = Part(libs.linear_sklib.linear, 'AD620')
---------------------------------------------------------------------------
AttributeError                            Traceback (most recent call last)
<ipython-input-2-18dcc70e8600> in <module>()
----> 1 AD620 = Part(libs.linear_sklib, 'AD620')

AttributeError: 'module' object has no attribute 'linear_sklib'

Also, search does not search the libs folder.

I'm using version 0.12, installed via pip.

Read field values of KiCad parts into Skidl definition

Hello,

I have a personal library of parts in a .lib file with the fields all filled out including the footprint, manufacturer name and no, distributor part no, etc.

It would be really great if Skidl could read in that information into fields when instantiating a part. I have to include that information into my KiCad library in order for KiCad to have the correct footprint for all my part symbols so the work is already done once.

Here's an example from my parts-lib.lib:

#
# NSR0240
#
DEF NSR0240 D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "NSR0240" 0 -100 50 H V C CNN
F2 "Diode_SMD:D_SOD-323" 50 -250 50 H I L CIN
F3 "https://datasheet.lcsc.com/szlcsc/ON-Semicon-ON-NSR0240HT1G_C152519.pdf" -150 -50 50 H I C CNN
F4 "NSR0240HT1G" 210 270 50 H I C CNN "Part No."
F5 "ON Semiconductor" 110 170 50 H I C CNN "Manufacturer"
F6 "LCSC" 110 170 50 H I C CNN "Distributor"
F7 "C152519" 110 170 50 H I C CNN "Distributor Part No."
F8 "Schottky (250mA Continuous Current) (.48V FVD) (.2uA @ 25V Reverse)" 110 170 50 H I C CNN "Description"
DRAW
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 N
P 6 0 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF

As you can see, the footprint is filled out, and with the LCSC order number, this library file is effectively an atomic library, I think it's called?

I was even thinking of adding an "in-stock" field to keep count of how many I have left. It would be easy to integrate a BOM generation tool that way.

F2 is always the footprint, F3 is always the datasheet, and then the other fields are the optional extra ones you can add but must name.

Add an "inspector" mode

An inspector mode would allow the perusal of the netlist prior to the termination of the SKiDL script. Possibly use the Python debugger and some helper functions for finding parts and examining their interconnections.

Import PySpice values to KiCad Netlist

When generating netlist with components having PySpice values (e.g. 3 @ u_Ohm) syntax error will occurs when you try import it in KiCad.

Adding quotes between {value} fix this problem.

https://github.com/xesscorp/skidl/blob/986fced89ce8f0bfc783f19fe6429ab01112f841/skidl/tools/kicad.py#L510

Separate meta data from instance data

Disclaimer: Skidl and Python noob ;-)

I would like an (optional) alternate way to instantiate parts. The duplication in the Part's constructor can be prevented by first creating a meta definition. This also allows a central definition of common used parts.

=>part-like constructor of meta data
partInfo1 = PartInfo(....)
partInfo2 = PertInfo(....)

=> no need to think about the specific part.
part1a = Part(partInfo1)
part1b = Part(partInfo1)
part2a = Part(partInfo2)
part2b = Part(partInfo2)

Subclassing 'Part' causes netlist issues

I realize that the TEMPLATE style is intended for this, but I believe that I want to add methods to certain part types.

The basic voltage-divider sample, as copied from the documentation:

from skidl import *

gnd = Net('GND') # Ground reference
vin = Net('VI') # Input voltage to the divider
vout = Net('VO') # Output voltage from the divider

r1, r2 = 2 * Part('device', 'R', TEMPLATE) # Create two resistors
r1.value, r1.footprint = '1K', 'Resistors_SMD:R_0805' # Set resistor values
r2.value, r2.footprint = '500', 'Resistors_SMD:R_0805' # and footprints

r1[1] += vin # Connect the input to the first resistor
r2[2] += gnd # Connect the second resistor to ground
vout += r1[2], r2[1] # Output comes from the connection of the two resistors

generate_netlist()

I am attempting to perform a simple subclass of Part that is specifically for resistors so that I can easily add methods specific to resistors. The same circuit:

from skidl import *

class Resistor(Part):
    def __init__(self, value, ref=None, footprint='Resistors_SMD:R_0805'):
        super().__init__('device', 'R', value=value, ref=ref, footprint=footprint)

gnd = Net('GND') # Ground reference.
vin = Net('VI')  # Input voltage to the divider.
vout = Net('VO')  # Output voltage from the divider.

r1 = Resistor('1k')
r2 = Resistor('500')

r1[1] += vin  # Connect the input to the first resistor.
r2[2] += gnd  # Connect the second resistor to ground.
vout += r1[2], r2[1]  # Output comes from the connection of the two resistors.

ERC()
generate_netlist()

In the attempt, I receive an error during netlisting. Up to the ERC(), all works great. The error:

ERROR: Can't generate netlist in an unknown ECAD tool format (<built-in function format>).
Traceback (most recent call last):
  File "C:\_virtualenv\skidl\lib\site-packages\skidl\skidl.py", line 1776, in _generate_netlist_component
    tool)]
KeyError: '_gen_netlist_comp_kicad'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
....
.... (more traceback)

Skidl is apparently seeting the ECAD tool format as incorrect when I subclass the Part. I suspect that there is a simple fix, but I am unsure as to how to proceed.

Thanks,

j

Combining Kicad and Skidl part libraries

I am not sure what I am doing wrong.

My default tool is KICAD and my search paths are like so:

lib_search_paths[KICAD].append('../library/snapEDA')
lib_search_paths[SKIDL].append('../library/skidl_lib')
lib_search_paths[KICAD].append('/usr/share/kicad/library')

in the SKIDL search path the part definition is in a file called gamete_lib.py.

The error I get is:

WARNING: Could not load KiCad schematic library "gamete", falling back to backup library.
Traceback (most recent call last):
  File "/home/alexander/.local/lib/python3.6/site-packages/skidl/tools/kicad.py", line 60, in _load_sch_lib_
    f, _ = find_and_open_file(filename, lib_search_paths_, lib_suffixes[KICAD])
  File "/home/alexander/.local/lib/python3.6/site-packages/skidl/utilities.py", line 290, in find_and_open_file
    logger, FileNotFoundError, "Can't open file: {}.\n".format(filename)
  File "/home/alexander/.local/lib/python3.6/site-packages/skidl/utilities.py", line 820, in log_and_raise
    raise exc_class(message)
FileNotFoundError: Can't open file: gamete.


During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "gamete.py", line 123, in <module>
    footprint='Package_TO_SOT_SMD:SOT-353_SC-70-5_HandSoldering',
  File "/home/alexander/.local/lib/python3.6/site-packages/skidl/Part.py", line 141, in __init__
    raise e
  File "/home/alexander/.local/lib/python3.6/site-packages/skidl/Part.py", line 131, in __init__
    lib = SchLib(filename=libname, tool=tool)
  File "/home/alexander/.local/lib/python3.6/site-packages/skidl/SchLib.py", line 99, in __init__
    load_func(filename, skidl.lib_search_paths[tool])
  File "/home/alexander/.local/lib/python3.6/site-packages/skidl/tools/kicad.py", line 64, in _load_sch_lib_
    filename, str(e)
FileNotFoundError: Unable to open KiCad Schematic Library File gamete (Can't open file: gamete.
)

The error looks like it is searching for a KICAD libary file. Do I have to change the default tool every time I search for a part that is in the other supported type? Skidl found previous Kicad parts that I instantiated.

Add ability to generate Eagle netlists.

Autocompletion (Definitely wishlist!)

I'm so in love with skidl so far! One thing I'd really love to see is some kind of autocompletion (maybe for visual studio code?) that knows about libraries and footprints.

Error with netlist_to_skidl

Installed from master, on jelly.net running:

netlist_to_skidl --input jelly.net --output jelly.py

Traceback (most recent call last):
  File "/home/kaspar/.local/bin/netlist_to_skidl", line 9, in <module>
    load_entry_point('skidl==0.0.12', 'console_scripts', 'netlist_to_skidl')()
  File "/home/kaspar/.local/lib/python2.7/site-packages/skidl/netlist_to_skidl_main.py", line 131, in main
    skidl_code = netlist_to_skidl(args.input[0])
  File "/home/kaspar/.local/lib/python2.7/site-packages/skidl/netlist_to_skidl.py", line 183, in netlist_to_skidl
    return _netlist_to_skidl(parse_netlist(netlist_src))
  File "/home/kaspar/.local/lib/python2.7/site-packages/skidl/parse_netlist.py", line 175, in parse_netlist
    return parse_func(text)
  File "/home/kaspar/.local/lib/python2.7/site-packages/skidl/parse_netlist.py", line 142, in _parse_netlist_kicad
    return parser.parseString(text)
  File "/home/kaspar/.local/lib/python2.7/site-packages/pyparsing.py", line 1632, in parseString
    raise exc
pyparsing.ParseException: Missing one or more required elements ({Suppress:("(") Suppress:("design") {[{Suppress:("(") Suppress:("source") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [{Suppress:("(") Suppress:("date") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [{Suppress:("(") Suppress:("tool") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [Group:({Group:({Suppress:("(") Suppress:("sheet") {{Suppress:("(") Suppress:("number") W:(0123...) Suppress:(")")} {Suppress:("(") Suppress:("name") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} {Suppress:("(") Suppress:("tstamps") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} [{Suppress:("(") Suppress:("title_block") {[{Suppress:("(") Suppress:("title") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [{Suppress:("(") Suppress:("company") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [{Suppress:("(") Suppress:("rev") {W:(0123...) [{"." [W:(0123...)]}]} Suppress:(")")}] & [{Suppress:("(") Suppress:("date") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [{Suppress:("(") Suppress:("source") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & Group:({Group:({Suppress:("(") Suppress:("comment") {{Suppress:("(") Suppress:("number") W:(0123...) Suppress:(")")} & {Suppress:("(") Suppress:("value") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}} Suppress:(")")})}...)} Suppress:(")")}]} Suppress:(")")})}...)]} Suppress:(")")}, {Suppress:("(") Suppress:("components") [Group:({Suppress:("(") Suppress:("comp") {{Suppress:("(") Suppress:("ref") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} & {Suppress:("(") Suppress:("value") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} & [{Suppress:("(") Suppress:("datasheet") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [{Suppress:("(") Suppress:("fields") [Group:({Suppress:("(") Suppress:("field") {{Suppress:("(") Suppress:("name") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} & {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}}} Suppress:(")")})]... Suppress:(")")}] & [{Suppress:("(") Suppress:("libsource") {{Suppress:("(") Suppress:("lib") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} & {Suppress:("(") Suppress:("part") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}} Suppress:(")")}] & [{Suppress:("(") Suppress:("footprint") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}] & [{Suppress:("(") Suppress:("sheetpath") {{Suppress:("(") Suppress:("names") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} & {Suppress:("(") Suppress:("tstamps") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}} Suppress:(")")}] & [{Suppress:("(") Suppress:("tstamp") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}]} Suppress:(")")})]... Suppress:(")")}, {Suppress:("(") Suppress:("nets") [Group:({Suppress:("(") Suppress:("net") {{Suppress:("(") Suppress:("code") W:(0123...) Suppress:(")")} & {Suppress:("(") Suppress:("name") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} & Group:({Group:({Suppress:("(") Suppress:("node") {{Suppress:("(") Suppress:("ref") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")} & {Suppress:("(") Suppress:("pin") {{string enclosed in double quotes ^ string enclosed in single quotes} ^ {Suppress:([<SPC><TAB><CR><LF>]...) !W:(()) Suppress:([<SPC><TAB><CR><LF>]...)}} Suppress:(")")}} Suppress:(")")})}...)} Suppress:(")")})]... Suppress:(")")}) (at char 19), (line:1, col:20)

xess.lib, pic32.lib and pickit3.lib referenced in tests/intfc_brd.py not in tree

xess.lib, pic32.lib and pickit3.lib referenced in tests/intfc_brd.py are not in tree, which makes tests fail.

When reference to xess.lib is changed from 'C:\xesscorp\KiCad\libraries\xess.lib' to './tests/pic32.lib' tests proceed, but fail in:

File "/Library/Frameworks/Python.framework/Versions/3.6/lib/python3.6/unittest/loader.py", line 153, in loadTestsFromName
    module = __import__(module_name)
  File "/Users/user/src/skidl/tests/intfc_brd.py", line 22, in <module>
    vreg['IN, EN'] += vusb
TypeError: unsupported operand type(s) for +=: 'NoneType' and 'Net'

I have MacOs 10.14.4 and Python 3.6.1

What is KISYSMOD environment variable

I found it mentioned here [0], but I have no clue what it's supposed to do and what to with it. I can see that you use it to find your libraries. But instead of using the given path you use something like /given/path/../library. I have installed kicad on my linux system and my libraries are located in ~/projects/kicad/lib. I think it's not a good idea to rely on the presence of this environment variable and then rely on the hard coded fact that libs are always in a directory called library.
If the environment variable is set up you may use it that way, but if it isn't there it should not trigger a warning (or make the program crash as shown in #10).
There should be an alternative way to present more paths to search for libraries. If you use KISYSMOD it should be well documented.

[0] https://xesscorp.github.io/skidl/docs/_site/blog/building-a-usb-to-jtag-interface-using-skidl

Gauging interest in ICT output.

If there are any readers involved in electronic manufacture, you are probably well aware of in-circuit-testing.

In circuit test uses a bed of nails and an (expensive) tester to get maximum coverage of a circuit board.

In order to begin this process, each in-circuit-tester has its own way of describing the netlist and the components on it.

I am vaguely interesting in giving skidl the ability to output "board" and "board_xy" files.

The board file describes everything electrical about the pcb.
The board_xy describes everything physical about the pcb.

@xesscorp would you be interested in this functionality? If you want, I can give you a document describing the syntax of a board and board_xy file.

install issues

Hi, I'm installing on Arch Linux as of 2016-09-10, and first I had slight nuisances installing:

1. Install failed on missing future module. No big deal, running pip install future fixes it, but I'd still say it should be included in requirements.txt
2. Install failed on missing KISYSMOD environment variable. I set it manually (even though I have KiCad installed) to /usr/share/kicad/modules, that seems to have fixed the issue.

Search with tool=SKIDL results in decode error

Works OK wihout tool=SKIDL (though it seems quite slow).

In [1]: from skidl import *

In [2]: search('resistor', tool=SKIDL)
                                         ERROR: 'utf8' codec can't decode byte 0xc2 in position 236: invalid continuation byte
---------------------------------------------------------------------------     
Exception                                 Traceback (most recent call last)
<ipython-input-4-6ec6c2287cd2> in <module>()
----> 1 search('resistor', tool=SKIDL)

./skidl/skidl.pyc in search(term, tool)
   3996 
   3997     term = '.*' + term + '.*' # Use the given term as a substring.
-> 3998     parts = search_libraries(term, tool)  # Search for parts with that substring.
   3999 
   4000     # Print each part name sorted by the library where it was found.

./skidl/skidl.pyc in search_libraries(term, tool)
   3972             for lib_file in lib_files:
   3973                 print(' '*79, '\rSearching {} ...'.format(lib_file), end = '\r')
-> 3974                 lib = SchLib(os.path.join(lib_dir,lib_file), tool=tool) # Open the library file.
   3975 
   3976                 def mk_list(l):

./skidl/skidl.pyc in __init__(self, filename, tool, **attribs)
    650                 # Use the tool name to find the function for loading the library.
    651                 load_func = getattr(self, '_load_sch_lib_{}'.format(tool))
--> 652                 load_func(filename, lib_search_paths[tool])
    653                 self.filename = filename
    654                 # Cache a reference to the library.

./skidl/skidl.pyc in _load_sch_lib_skidl(self, filename, lib_search_paths)
    781         except Exception as e:
    782             logger.error(e)
--> 783             raise Exception
    784 
    785     def add_parts(self, *parts):

Merging two Nets with PySpice GND Net('0')

The error was occurring in simulation when Net('0') merges with a different name.
https://github.com/xesscorp/skidl/blob/467230c8fba9caad429b6ca18ba5f21af3b4f87b/skidl/Net.py#L537

Checking for GND Net('0') fix the problem:

if nets[1].name == '0':  
    return nets[1]

ERROR: No footprint for ATMEGA16U2-MU/U4.

When executing this SKiDL program, I get the following errors:

ERROR: No footprint for RESET_SWITCH/SW1.
ERROR: No footprint for LD1117S50TR/U1.
ERROR: No footprint for LM358/U2.
ERROR: No footprint for ATMEGA16U2-MU/U4.

0 warnings found during netlist generation.
4 errors found during netlist generation.

Then, I do a search for ATMEGA16U2-MU and the final lines tell me this.

MCU_Microchip_ATmega.lib: ATmega8U2-MU (16MHz, 8kB Flash, 512B SRAM, 512B EEPROM, QFN-32)

So I suppose the component is included in the libraries, including footprint.

What would be the correct way to troubleshoot problems like that, of missing components or footprints?

Implement resistance, capacitance and inductance functions

These functions would take RLC values and turn them into strings that can be stored in the value attribute of Part objects. Companion functions to turn the strings back into floating-point numbers would be good as well. And these should work with standardized values for various component tolerances.

Bit confused about `Bus`

I have some questions regarding buses. I feel I understand buses in schematics but I haven't used them very much. In the context of SKiDL I don't understand:

• What does a bus provide as opposed to a list of nets?
• Why do you specify the width of a bus if it's dependent on the number of nets in it?
• Why do buses need to be named?

Apply external power to net to satisfy ERC

I have a circuit with some input pins and power supplied externally.
So ERC thinks there is nothing that drives these nets and complains.
I don't want to completely disable ERC for that net, I just want to tell it I will connect something to it.

In Kicad there is PWR_FLAG, which silences the warning, but then of course when you make a netlist it complains it has no footprint.

Is there a way to do this?