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Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5

Home Page: http://www.gem5.org

License: BSD 3-Clause "New" or "Revised" License

Shell 0.17% Ruby 0.01% C++ 75.86% Python 15.01% Perl 0.04% C 7.75% Emacs Lisp 0.01% Java 0.01% Scala 0.01% Fortran 0.03% SuperCollider 0.02% Assembly 0.25% Awk 0.01% Forth 0.01% Hack 0.13% Makefile 0.07% HTML 0.25% CMake 0.24% M4 0.07% Dockerfile 0.07%
microarchitecture prefetching simulator

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gem5-fdp's Issues

memory leak risk

if (cacheSnoop && (inCache(pkt->getAddr(), pkt->isSecure())
|| (inMissQueue(pkt->getAddr(), pkt->isSecure())))) {
stats.pfInCache++;
DPRINTF(HWPrefetch, "Drop Packet. In Cache / MSHR\n");
return;
}

delete pkt; should be added before return.

how to ensure the pc will NOT advanced twice in BAC::updatePreDecode

Hi sir:

when I read the source code of the BAC, I found that there are chances that the fetch pc be advanced twice !?
the 1st advance is at L876 when we reach the line with hist == nullptr which is the normal case
and in this situation the target_set is not set (and remains false ), and hist->predTaken is set to false
then the flow will continue and reach the line 985 where the pc is advance second time !!

is that right?
or do I miss something important that will change the flow above so that the flow above will never happend ?

hope your informations, thanks~

inst->advancePC(*hist->target);

inst->advancePC(pc);

High host CPU memory requirement

Hello,
I ran tuned ARM cpu full system simulation for a large workload (that takes 8 hours on a supercomputer) using gem5-dev branch code.
However, with this commit, sometimes my job is killed which I think is due to excessive memory requirement. If I run a small workload then it works fine. Could you identify or estimate, where can we improve memory management in terms of the implementation of fdp and/or the associative BTB?

I changed associative BTB to simpleBTB_v2 like below:

namespace branch_prediction
{

SimpleBTB::SimpleBTB(const SimpleBTBParams &p)
    : BranchTargetBuffer(p),
        numEntries(p.numEntries),
        tagBits(p.tagBits),
        instShiftAmt(p.instShiftAmt),
        log2NumThreads(floorLog2(p.numThreads))
{
    DPRINTF(BTB, "BTB: Creating BTB object.\n");

    if (!isPowerOf2(numEntries)) {
        fatal("BTB entries is not a power of 2!");
    }

    btb.resize(numEntries);

    for (unsigned i = 0; i < numEntries; ++i) {
        btb[i].valid = false;
    }

    idxMask = numEntries - 1;

    tagMask = (1 << tagBits) - 1;

    tagShiftAmt = instShiftAmt + floorLog2(numEntries);
}

void
SimpleBTB::memInvalidate()
{
    for (unsigned i = 0; i < numEntries; ++i) {
        btb[i].valid = false;
    }
}

inline
unsigned
SimpleBTB::getIndex(Addr instPC, ThreadID tid)
{
    // Need to shift PC over by the word offset.
    return ((instPC >> instShiftAmt)
            ^ (tid << (tagShiftAmt - instShiftAmt - log2NumThreads)))
            & idxMask;
}

inline
Addr
SimpleBTB::getTag(Addr instPC)
{
    return (instPC >> tagShiftAmt) & tagMask;
}

SimpleBTB::BTBEntry *
SimpleBTB::findEntry(Addr instPC, ThreadID tid)
{
    unsigned btb_idx = getIndex(instPC, tid);
    Addr inst_tag = getTag(instPC);

    assert(btb_idx < numEntries);

    if (btb[btb_idx].valid
        && inst_tag == btb[btb_idx].tag
        && btb[btb_idx].tid == tid) {
        return &btb[btb_idx];
    }

    return nullptr;
}

bool
SimpleBTB::valid(ThreadID tid, Addr instPC)
{
    BTBEntry *entry = findEntry(instPC, tid);

    return entry != nullptr;
}

// @todo Create some sort of return struct that has both whether or not the
// address is valid, and also the address.  For now will just use addr = 0 to
// represent invalid entry.
const PCStateBase *
SimpleBTB::lookup(ThreadID tid, Addr instPC, BranchType type)
{
    stats.lookups[type]++;

    BTBEntry *entry = findEntry(instPC, tid);

    if (entry) {
        return entry->target.get();
    }
    stats.misses[type]++;
    return nullptr;
}

const StaticInstPtr
SimpleBTB::lookupInst(ThreadID tid, Addr instPC)
{
    BTBEntry *entry = findEntry(instPC, tid);

    if (entry) {
        return entry->inst;
    }
    return nullptr;
}

void
SimpleBTB::update(ThreadID tid, Addr instPC,
                    const PCStateBase &target,
                    BranchType type, StaticInstPtr inst)
{
    unsigned btb_idx = getIndex(instPC, tid);

    assert(btb_idx < numEntries);

    stats.updates[type]++;

    btb[btb_idx].tid = tid;
    btb[btb_idx].valid = true;
    set(btb[btb_idx].target, target);
    btb[btb_idx].tag = getTag(instPC);
    btb[btb_idx].inst = inst;
}

} // namespace branch_prediction
} // namespace gem5

Try to run spec2017 has error:AttributeError: Class HPI_BP has no parameter 'BTBEntries'

Hi sir:
I want to run spec2017 based on fdp-hello.py.Part of my configuration is like this:

from m5.util import addToPath
addToPath("../")
from common import Options
Options.addCommonOptions(parser)
Options.addSEOptions(parser)

I need to use --warmup-insts=1000000 -I 2000000 because spec2017 is too large.When I run the script I get the error:

AttributeError: Class HPI_BP has no parameter 'BTBEntries'

At:
  src/python/m5/SimObject.py(408): __setattr__
  src/python/m5/SimObject.py(293): __init__
  /home/ronnie/Projects/riscv-fs/gem5-fdp/configs/common/cores/arm/HPI.py(1682): <module>

But HPI_BP has BTBEntries.How can I solve this?Or can this build FDP based on gem5-fdp/configs/deprecated/example/se.py?
Hope for your information!Thanks~

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