dineshannayya Goto Github PK

8bit_dac

4 x 8 Bit DAC taget to openroad/openlane flow and sky130 foundary

actions-test

openlane action scripts

ahb3lite_interconnect

AHB3-Lite Interconnect

arduino-library-registry

Arduino Library Manager list

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

cache

Memory Mapped Cache

digispark-attiny85

Riscduino Integration with DigiSpark-ATTINY85

dineshannayya

Config files for my GitHub profile.

dockerized-verification-setup

This is a dockerized tool chain for running verilog DV customized for the sky130A-based projects.

foss_labs

VLSI lab for foss

fpu

IEEE 754 floating point unit in Verilog

lighter

An automatic clock gating utility

logic_bist

mbist_ctrl

https://caravel-user-project.readthedocs.io

openframe_riscduino_dcore

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openocd_ch347

OpenOCD Source code for waveshare CH347

openram

An open-source static random access memory (SRAM) compiler.

qspim

SPI Master Optimized for RISC V Instruction memory Prefecth

qspis

Single,Dual and Quad SPI Slave

rdnodude

riscduino_dude is a utility to program riscduino based SOC

riscduino

Arduino compatible Risc-V Based SOC

riscduino-docs

Riscdunio Project Documentation

riscduino_board

Riscduino PCB Board documentation

riscduino_bringup

Host all the MPW Bring-up related Enviornment

riscduino_dcore

riscduino_dcore_gf180

Riscduino Dual core target to GF180nm

riscduino_examples

Repository for Riscduino Examples

riscduino_firmware

Repository for storing Arduino related files and custom board definition.

riscduino_mcufriend_kbv

MCUFRIEND_kbv Library for Arduino and Riscduino Uno 2.4, 2.8, 3.5, 3.6, 3.95 inch mcufriend Shields