dineshannayya/riscduino

Arduino compatible Risc-V Based SOC

riscduino's Issues

Discrepencies in the readme.

Hi.

Your readme says this:

Step-2: Clone , update the Submodule, unzip the content

   git clone https://github.com/dineshannayya/riscduino.git
   cd riscduino
   git submodule init
   git submodule update
   make unzip

but the commands don't do what is expected. has there been an update which has not been reflected in this readme ?
make unzip complains about lef/*.gz files being missing. Is there something im missing?

Thanks in advance!

About caravel soc wishbone protocol

Just to confirm, which version of the wishbone bus protocol was written according to when RISCDUINO was designed? I didn't see more detailed version information in the caravel SOC. Will the B4 version works?

BRs,
Yuxiang

Where to buy a riscduino board?

Hi, I would like to buy a riscduino sample board. Where can I get it?

Die status

I saw, in e-fabless website, that your project tape-out has been done properly. I am wondering that did your chip run flawlessly in real world?

About the change of FP_SIZING from ABSOLUTE to RELATIVE

###############################################################
Hello dear professor, what changes do I need to be aware of when FP_SIZING changes from absolute to relative, apart from the config.tcl configuration? Things like sdc files etc

Did you download the latest version of your riscduino, which is the latest openroad tool? Also I'm having some problems with make

I've had the same problem as you before, you asked it at openlane, see this URL.
##################URL###########################PDN--MACRO--HALO###############
···https://github.com/The-OpenROAD-Project/OpenLane/issues/1262···

I need to download the latest version of openroad tools, is it git pull your new version of riscduino and I'm good to go?
I get the following error when I make
#########error#######################
###############################################
sh: flow.tcl: command not found
make: *** [Makefile:44: user_project_wrapper] Error 127

issue with openlane root of riscvduino

hello sir,
i wanted run the design by installing riscvduino n i skipped step 1 as i already have Docker version 20.10.21, build 20.10.21-0ubuntu1~22.04.3

i have git cloned this riscvduino as this repo directed,but
in rtl to gds flow
i coudnt able make pinmux or just make ,as it says this issue

how can i fix "export openlane root"

is this bcz of i skipped step 1, {i left it, as -agent in second line of step 1 is an error}
can you please help me as im very new to these things.

question about clock skew adjust

PDN probelm

I have now put all the Verilogs together to run a macro, but have encountered a problem, reporting the following error
#############ERROR###############################
[STEP 6]
[INFO]: Running Tap/Decap Insertion...
[INFO]: Connecting Power: vccd1 & vssd1 to All internal macros.
[INFO]: Generating PDN...
[ERROR]: PDN generation failed.
[ERROR]: You may need to adjust your macro placements or PDN offsets/pitches to power all standard cell rails (or other PDN stripes) in your design.
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'user_project_wrapper/runs/user_project_wrapper/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'user_project_wrapper/runs/user_project_wrapper/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.

#########################config.tcl###############################################
set ::env(PDK) "sky130A"
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"

YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS

source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl

YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL

source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl

set script_dir [file dirname [file normalize [info script]]]
set proj_dir [file dirname [file normalize [info script]]]

set ::env(ROUTING_CORES) "6"

set ::env(DESIGN_NAME) user_project_wrapper
set verilog_root $proj_dir/../../verilog/

User Configurations

set ::env(DESIGN_IS_CORE) 1
set ::env(FP_PDN_CORE_RING) 1

Source Verilog Files

set ::env(VERILOG_FILES) "
$proj_dir/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv
$proj_dir/../../verilog/rtl/user_project_wrapper.v
$script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
$script_dir/../../verilog/rtl/pinmux/src/pinmux.sv
$script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv
$script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv
$script_dir/../../verilog/rtl/pinmux/src/pwm.sv
$script_dir/../../verilog/rtl/pinmux/src/timer.sv
$script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv
$script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv
$script_dir/../../verilog/rtl/lib/registers.v
$script_dir/../../verilog/rtl/lib/ctech_cells.sv \

$script_dir/../../verilog/rtl/lib/reset_sync.sv      \
$script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_regs.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_fifo.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_clkgen.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_ctrl.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_rx.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_tx.sv	\

$script_dir/../../verilog/rtl/uart/src/uart_core.sv  \
$script_dir/../../verilog/rtl/uart/src/uart_cfg.sv   \
$script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
$script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
$script_dir/../../verilog/rtl/lib/async_wb.sv   \
$script_dir/../../verilog/rtl/lib/async_fifo.sv      \
$script_dir/../../verilog/rtl/lib/async_fifo_th.sv   \
$script_dir/../../verilog/rtl/lib/double_sync_low.v  \
$script_dir/../../verilog/rtl/lib/clk_ctl.v          \
$script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v      \
$script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v     \
$script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v           \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_core.sv    \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv   \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv    \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv    \  
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv     \
$script_dir/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v     \
$script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
$script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv     \
$script_dir/../../verilog/rtl/sspim/src/sspim_top.sv             \
$script_dir/../../verilog/rtl/sspim/src/sspim_ctl.sv             \
$script_dir/../../verilog/rtl/sspim/src/sspim_if.sv              \
$script_dir/../../verilog/rtl/sspim/src/sspim_cfg.sv             \
$script_dir/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\

$script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
$script_dir/../../verilog/rtl/lib/async_reg_bus.sv   \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv     \
$script_dir/../../verilog/rtl/uart2wb/src/uart2wb.sv \
$script_dir/../../verilog/rtl/uart2wb/src/uart2_core.sv \
$script_dir/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \

$script_dir/../../verilog/rtl/lib/sync_wbb.sv                \
$script_dir/../../verilog/rtl/lib/sync_fifo2.sv                \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv  \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \

$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_core_top.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dm.sv                          \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_scu.sv                         \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc.sv                        \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv              \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dmi.sv                         \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv      \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv          \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv          \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv               \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv               \

$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv                  \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv                 \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_router.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv                \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv                   \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_tcm.sv                        \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_timer.sv                      \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_arb.sv                     \

    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv            \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv       \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv       \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv            \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv        \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv                      \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_intf.sv                        \
$script_dir/../../verilog/rtl/digital_pll/src/digital_pll_controller.v  \
$script_dir/../../verilog/rtl/digital_pll/src/digital_pll.v             \
$script_dir/../../verilog/rtl/digital_pll/src/ring_osc2x13.v    \
"

Black-box verilog and views

set ::env(VERILOG_FILES_BLACKBOX) "
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v
"

set ::env(EXTRA_LEFS) "
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef
"
set ::env(EXTRA_GDS_FILES) "
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds
"

Clock configurations

set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
set ::env(CLOCK_PERIOD) "10"

set ::env(SYNTH_MAX_FANOUT) 4

CTS BUFFER

set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_16 "
set ::env(CTS_SINK_CLUSTERING_SIZE) "
16
50
"
set ::env(CLOCK_BUFFER_FANOUT) "
8
20
"
set ::env(LEC_ENABLE) 0

set ::env(VERILOG_INCLUDE_DIRS) "
[glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
[glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
[glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
[glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
[glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ]
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]

set ::env(SDC_FILE) "\
$script_dir/base.sdc
$script_dir/pinmux.sdc
$script_dir/qspim.sdc
$script_dir/uart_i2cm_usb_spi_top.sdc
$script_dir/wb_host.sdc
$script_dir/wb_interconnect.sdc
$script_dir/ycr_core_top.sdc
$script_dir/ycr_iconnect.sdc
$script_dir/ycr_intf.sdc
"
set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"

set ::env(VDD_PIN) [list {vccd1}]
set ::env(GND_PIN) [list {vssd1}]

set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}

Floorplan

set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SZING) absolute

set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
set ::env(PL_TARGET_DENSITY) 0.4
set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl

set ::env(RT_MAX_LAYER) {met5}

set ::env(FP_PDN_CHECK_NODES) 0

set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 3

set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
set ::env(QUIT_ON_MAGIC_DRC) "1"
set ::env(QUIT_ON_LVS_ERROR) "1"
set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"

#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"

set ::env(RUN_CVC) 0

set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0

Macro PDN Connections

set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"

set ::env(GLB_RT_OBS) "
li1 150 130 833.1 546.54,
met1 150 130 833.1 546.54,
met2 150 130 833.1 546.54,
met3 150 130 833.1 546.54,
li1 950 130 1633.1 546.54,
met1 950 130 1633.1 546.54,
met2 950 130 1633.1 546.54,
met3 950 130 1633.1 546.54,
li1 150 750 833.1 1166.54,
met1 150 750 833.1 1166.54,
met2 150 750 833.1 1166.54,
met3 150 750 833.1 1166.54,\
met5 0 0 2920 3520"

set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"

###PDN offset and pitch
set ::env(FP_IO_VEXTEND) 4
set ::env(FP_IO_HEXTEND) 4

set ::env(FP_PDN_VPITCH) 100
set ::env(FP_PDN_HPITCH) 100
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5

set ::env(FP_PDN_VOFFSET) "5"
set ::env(FP_PDN_HOFFSET) "10"

set ::env(FP_PDN_HORIZONTAL_HALO) "10"
set ::env(FP_PDN_VERTICAL_HALO) "10"

set ::env(FP_PDN_VSPACING) "15.5"
set ::env(FP_PDN_HSPACING) "10"

caravel soc & riscduino soc memory mapping

Is the Uart Master in the diagram a new addition to the RISCDUINO core? Seems like it‘s another uart input directly connected to the package pin.
Actually we are planning to build a new project based on the RISCDUINO for open-mpw flow, but we have found that the memory mapping of the caravel soc and the riscduino soc are not the same. What is the basis for this? If we change the memory mapping of riscduino to match the caravel soc, what needs to be changed?

BRs
Yuxiang

RISCV compilation in macOS Apple Silicon

While compiling getting this error:

Running in virtual ubuntu in Apple Silicon.

WARNING: The requested image's platform (linux/amd64) does not match the detected host platform (linux/arm64/v8) and no specific platform was requested
exec /usr/bin/sh: exec format error
make: *** [Makefile:43: user_analog_project_wrapper] Error 1

Error while running riscv_regress test

Hello,
I am running riscv_regress test using make verify-riscv_regress command.
I am getting error as below,

In C-ANDI.S file, It showing illegal operands error in line number 50, 63, 76, 89 and 102. (i.e., TEST_CI_OP(c.andi, x11, 0x0, 0x0, 0x0, x2, 0), TEST_CI_OP(c.addi, x12, 0x2, 0x1, 0x1, x2, 0), TEST_CI_OP(c.addi, x17, 0, -0x1, 0x1, x2, 0), TEST_CI_OP(c.addi, x22, 0x80000, 0x7ffff, 0x1, x2, 0), TEST_CI_OP(c.addi, x27, 0x80001, 0x80000, 0x1, x2, 0)

Even in riscduino/verilog/dv/riscv_regress/dependencies/riscv-tests/isa/rv64si/csr.s file, for the instruction csrwi it is showing **Instruction csrwi requires absolute expression **.

Compiling ../../../common/vpi/system/system.c...
../../../common/vpi/system/system.c: In function 'system_compiletf':
../../../common/vpi/system/system.c:4:34: warning: unused parameter 'user_data' [-Wunused-parameter]
4 | static int system_compiletf(char*user_data)
| ~~~~~^~~~~~~~~
../../../common/vpi/system/system.c: In function 'system_calltf':
../../../common/vpi/system/system.c:33:7: warning: implicit declaration of function 'system' [-Wimplicit-function-declaration]
33 | system(value_s.value.str);
| ^~~~~~
../../../common/vpi/system/system.c: At top level:
../../../common/vpi/system/system.c:37:6: warning: function declaration isn't a prototype [-Wstrict-prototypes]
37 | void system_register()
| ^~~~~~~~~~~~~~~
../../../common/vpi/system/system.c:50:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
50 | void (*vlog_startup_routines[])() = {
| ^~~~
Making system.vpi from system.o...
/bin/sh: 9: : not found
make: *** [Makefile:280: run_iverilog] Error 127
make: *** [Makefile:130: verify-riscv_regress] Error 2

Please help me out to run this test successfully.

Issue with the installation of docker

The command provide on the page is not working
sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
correct command is as follows
sudo apt-get install apt-transport-https curl ca-certificates software-properties-common

Document ADC Shortcomings

The block diagram on the front page lists a 6-channel ADC as being one of the features, and there are RTL files that appear to implement a SAR-ADC. However, there are multiple places that state that the ADC is "In progress - looking for community help".

What is the state of this block? Is it waiting for characterization? Is it not included in any files? Or is it included and the documentation just needs to be updated?

PDK path error

I have installed pdk in a specific directory and I export it as $PDK_ROOT. However, when I run make verify-.. test scenario, I get /opt/pdk/sky130A not found, please install pdk before running make. error. I changed the PDK_ROOT path, where in wb-port's Makefile, to absolute path and run make verify-wb_port. Yet, there was another error occured like below lines.

Include file libs.ref/sky130_fd_sc_hd/verilog/primitives.v not found
No top level modules, and no -s option.

access latency about the sky130_sram?

From the waveform I see there are 2 access latency when reading the sky130_sram, can I have 1 clock latency sky130 sram?

riscduino soc

The riscduino is a great project, but after learning about it, I still have some confusion.

Is there a relevant FPGA test routine for the riscduino SOC?
There are some differences between the memory map of riscduino SOC and the memory map of caravel SOC. For example, 0x1000_0000 is QSPI config reg for riscduino and flash spi for caravel, what is the reason for this?

linting issue

linter.log
hello sir , i was runnig rtl to gds flow using openlane , but in am getting linter issue , could you please help me to take care of it .

SystemVerilog support by yosys

When I was using openlane, I found that yosys has poor support for SystemVerilog, for example, the defined typedef struct packed cannot be used in the module declaration. However, I see that your project uses SystemVerilog typedef grammar, how is this synthesized by yosys?

It feels like there is something wrong with the code（openlane/pinmux/config.tcl.tcl）

########/openlane/pinmux/config.tcl#################

set ::env(FP_IO_VEXTEND) {6}
set ::env(FP_IO_HEXTEND) {6}

set ::env(FP_IO_VEXTEND) 4
set ::env(FP_IO_HEXTEND) 4

Would these two paragraphs be duplicated?

When I try to open the def\lef file with <openroad>, I have problems

############instruction##############################
openroad> read_lef user_project_wrapper.lef

############problem##################################
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met3) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced
[WARNING ODB-0176] error: undefined layer (met2) referenced

#############instruction###############################
openroad> read_def ../def/user_project_wrapper.def

#############problem###############################
[INFO ODB-0127] Reading DEF file: ../def/user_project_wrapper.def
[INFO ODB-0128] Design: user_project_wrapper
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_0) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_1) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_2) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_3) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_4) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_5) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_6) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_7) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_8) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_9) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_10) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_11) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_12) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_13) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_14) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_15) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_16) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_17) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_18) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_19) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_20) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_21) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_22) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_23) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_24) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_25) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_26) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_27) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_28) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_29) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_30) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_31) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_32) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_33) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_34) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_35) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_36) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_37) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_38) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_39) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_40) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_41) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_42) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_43) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_44) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_45) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_46) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_47) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_48) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_49) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_50) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_51) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_52) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_53) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_54) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_55) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_56) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_57) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_58) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_59) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_60) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_61) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_62) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_63) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_64) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_65) statement.
[WARNING ODB-0155] error: undefined site (unithd) referenced in row (ROW_66) statement.

Discrepencies in the readme.

In the SOC Pin Mapping Section of the README, the diagram and table values do not match.

ATMEGA328 Pin No 1 in the diagram is connected to Arduino Digital Pin 22 (D22) but in the the Table right below it, its D20.

Similiarly, there is mismatches at PINS 9 and 10.

Upon closer observation, one can notice that these are only for Arduino functions (reset and crystal) which aren't defined by specification. ATmega168/328P-Arduino Pin Mapping

Can you please clarify which of these is the correct pin mapping?

openlane/Module call problem

When "make user_project_wrapper", its config. tcl file does not contain all verilog files, but only top and its next level. Why can it run all of them?

===================================code==================================

Source Verilog Files

set ::env(VERILOG_FILES) "
$proj_dir/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv
$proj_dir/../../verilog/rtl/user_project_wrapper.v"

Black-box verilog and views

set ::env(VERILOG_FILES_BLACKBOX) "
$proj_dir/../../verilog/gl/qspim_top.v
$proj_dir/../../verilog/gl/wb_interconnect.v
$proj_dir/../../verilog/gl/pinmux.v
$proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v
$proj_dir/../../verilog/gl/wb_host.v
$proj_dir/../../verilog/gl/ycr_intf.v
$proj_dir/../../verilog/gl/ycr_core_top.v
$proj_dir/../../verilog/gl/ycr_iconnect.v
$proj_dir/../../verilog/gl/digital_pll.v
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v
"

=================================instruction==================================
make user user_project_wrapper

Problems with ‘make user_project_wrapper'

####################error#######################################
OpenLane UNKNOWN
(with mounted scripts from couldn't create error file for command: permission denied)
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

couldn't create error file for command: permission denied

Openlane implementation error

I updated my docker by replacing mpw5 in your docker repo. I got running simulation except spi that fails. However, when I run make command in openlane folder or make user_project_wrapper in riscdunio root path I got error about some path which I do not have.

Error: sta.tcl, 126 can't read "::env(CLOCK_PORT)": no such variable
[ERROR]: during executing: "openroad -exit /openlane/scripts/openroad/resizer.tcl |& tee >&@stdout /project/openlane/clk_skew_adjust/runs/clk_skew_adjust/logs/placement/7-resizer_design_optimization.log"

Run Directory: /project/openlane/clk_skew_adjust/runs/clk_skew_adjust                                                                                                                                                                      
Source not found.

Source: /project/openlane/clk_skew_adjust/runs/clk_skew_adjust/results/lvs/clk_skew_adjust.lvs_parsed.gds.log                                                                                                                              
Source not found.

[INFO]: check full report here: /project/openlane/clk_skew_adjust/runs/clk_skew_adjust/reports/final_summary_report.csv
[INFO]: Saving Runtime Environment

There is no path which begins with project in my directories. Is there any solution about it ? Thanks for your previous quick replies btw.

FPU Integration

A thread to discuss ideas and changes required to integrate FPU from https://github.com/dineshannayya/fpu into Riscduino

MPW-5 single core git version

How do I get your MPW-5 single core git version?
If i understand correctly, all your MPW code in the same git repo, same branch(master), How do I get different MPW version code? is that possible?

BRs
luping

How can I program the RISCDUINO SOC?

I saw this RISCDUINO SoC project on the efabless website and it blew up my mind so interestingly I landed upon your GitHub page. I have a set of questions in my mind which are as follows:

Q.1: Have you received and tested the RISCDUINO?
Q.2: How can I burn the program in RISCDUINO?
Q.3: What are the tools (compilers, IDE, etc) required to build the firmware? I've seen that you are working on integration with Arduino IDE but also fails to find any solution for windows. is there any other possible way to carry on the development with windows?

Clock speed?

Such a cool project!

How many MHz is the RISC-V core?

Thanks!