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Org_lab

计算机组成实验/Project Teacher: SQS

计算机体系结构lab Teacher: KG

正好被迫摸鱼,509的恶劣环境也不适合学习。

用全verilog重新整合一下要验收的几次实验,以及sqs及其折磨人的两次project。

啊这啊这啊这 因为体系课程需要所以7,12改成了玉泉板子xixi

进度:

  • Lab3 -- 顶层架构

  • Lab7 -- 单周期CPU

  • Lab12 -- 多周期CPU

  • Pro1 -- MIPS

  • Pro2 -- MIPS + CPU 👴懒了 自己去gitee找demo吧


  • Lab8 -- 中断 看心情(鸽

  • Lab7 仿真 看心情(鸽

  • Lab12 仿真 看心情(鸽

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