eecysu/graflex

[FPGA 2024] GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network

GraFlex

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network

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Code Structure

• applications -> Example implementations of graph applications
• automation -> Python scripts to generate Tcl scripts for GraFlex automation flow
• UTIL_IP -> Infrastructure IP library packaged with Vivado 2020.2

Prerequisites

Software

• Python >= 3.7
• Vivado & Vitis & Vitis HLS 2020.2
• XRT Version: xrt_202110.2.11.634 or xrt_202020.2.8.743 (newer ones not verified)

Hardware

• AMD Xilinx Alveo U280 Acceleration Board

Quick Start (Check the GraFlex_AutoDemo.mp4 video for example)

Try GraFlex with the BFS example (Bellman-Ford, 2 PEs)

Step 1: Generate Tcl Scripts for Automation

cd <path_to>/GraFlex/applications/bfs_bf/PE_2
export PYTHONPATH=<path_to>/GraFlex/automation
python auto_backend.py

Step 2: Invoke Tcl Scripts from Vivado

vivado -source autoTcl/auto_backend.tcl

Step 3: Wait for Vivado to Finish Synthesis and Generate Compilable Object (.xo)

Step 4: Compile the Object with Vitis v++

Check applications/bfs_bf/PE_2/xo2xclbin for example

Artifact Evaluation

Current release is not fully stable. To access the graph datasets and directly reproduce the results, please visit the following Zenodo link:

Cite this work

If you use this work in your paper, please cite our work here.

@inproceedings{su2024graflex,
  title={GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network},
  author={Su, Chunyou and Du, Linfeng and Liang, Tingyuan and Lin, Zhe and Wang, Maolin and Sinha, Sharad and Zhang, Wei},
  booktitle={Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays},
  pages={143--153},
  year={2024}
}