enjoy-digital/litex

Build your hardware, easily!

litex's Issues

Add multi-core support

AttributeError: 'set' object has no attribute 'specials'

I'm guessing a bad merge?

make: Leaving directory `/home/travis/build/mithro/litex/soc_basesoc_versa_ecp5/software/bios'
Traceback (most recent call last):
  File "/home/travis/miniconda/envs/litex/lib/python3.6/runpy.py", line 193, in _run_module_as_main
    "__main__", mod_spec)
  File "/home/travis/miniconda/envs/litex/lib/python3.6/runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "/home/travis/build/mithro/litex/litex/boards/targets/versa_ecp5.py", line 93, in <module>
    main()
  File "/home/travis/build/mithro/litex/litex/boards/targets/versa_ecp5.py", line 89, in main
    builder.build()
  File "/home/travis/build/mithro/litex/litex/soc/integration/builder.py", line 171, in build
    toolchain_path=toolchain_path, **kwargs)
  File "/home/travis/build/mithro/litex/litex/soc/integration/soc_core.py", line 403, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/travis/build/mithro/litex/litex/build/lattice/platform.py", line 29, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/travis/build/mithro/litex/litex/build/lattice/trellis.py", line 152, in build
    top_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/home/travis/build/mithro/litex/litex/build/lattice/platform.py", line 26, in get_verilog
    **kwargs)
  File "/home/travis/build/mithro/litex/litex/build/generic_platform.py", line 368, in get_verilog
    create_clock_domains=False, **kwargs)
  File "/home/travis/build/mithro/litex/litex/gen/fhdl/verilog.py", line 380, in convert
    fs, lowered_specials = lower_specials(special_overrides, f.specials)
  File "/home/travis/miniconda/envs/litex/lib/python3.6/site-packages/migen/fhdl/tools.py", line 352, in lower_specials
    fs, lowered_specials_step = _lower_specials_step(overrides, f.specials)
AttributeError: 'set' object has no attribute 'specials'
The command "./.travis-build-socs.sh" exited with 1.

Accessing unmapped Wishbone address freezes system

The Wishbone bus is sparsely populated, and contains many unmapped addresses. Attempting to access one of these addresses locks up the system.

There are at least two issues here:

1. There is nothing listening on the "null" cyc line, so there is no default listener
2. The current Wishbone architecture assumes transactions are always successful, and will wait forever if a slave pulls err.

For (1), it should be a simple matter of coming up with a signal that feeds into the err (or ack) signal on Wishbone that is (~(slave[0].cyc | slave[1].cyc | ... | slave[n].cyc) & slave.stb), such that a response signal is generated immediately upon access to an unmapped address.

For (2), the state machine will need to be modified somewhat to return to the IDLE state if err is hit, or however Wishbone is supposed to handle error conditions.

Because (1) is much easier to do than (2), it may be easier to have invalid accesses return bogus data than to have invalid accesses return an error condition. Either way, it would be nice to not have Wishbone lock up when accessing an invalid address.

Fails to build bios with --with-ethernet flag

sniped output of arty.py --cpu-type picorv32 --with-ethernet

`macadr' referenced in section `.text' of boot.o: defined in discarded section `.sdata' of boot.o
`macadr' referenced in section `.text' of boot.o: defined in discarded section `.sdata' of boot.o
`broadcast' referenced in section `.text' of ../libnet/libnet.a(microudp.o): defined in discarded section `.sdata' of ../libnet/libnet.a(microudp.o)
`broadcast' referenced in section `.text' of ../libnet/libnet.a(microudp.o): defined in discarded section `.sdata' of ../libnet/libnet.a(microudp.o)

This can be fixed by moving the line: *(.sdata .sdata.* .gnu.linkonce.s.*) from the discard section to the text section of the linker script. Poking around in the history of the linker script, it looks like data sections are undesireable. I'm not sure why that is the case, or if this is breaking whatever rule or design goal was behind that.

CSRs in VexRiscv are violating the priv spec

VexRiscv defines two registers that were added as a plugin specially for LiteX:

csr.rw(0x330, mask)
csr.r(0x360, pendings)

In my opinion both violate the priv spec (both 1.9 and 1.10).
0x330 is the most problematic as it violates this definition:

#define CSR_MHPMEVENT16 0x330

It is easy to spot by issuing this:

riscv64-unknown-elf-objdump -S bios.elf | grep mhpmevent16

While I understand that you could always say that a cpu does not follow priv spec at all, I would still suggest to follow it at least to a point of using ranges that are meant for custom CSRs (see Table 2.1: Allocation of RISC-V CSR address ranges. on page 8 in the spec: https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.1.pdf).

There are two benefits of that:

• disassembly using a standard riscv gcc will make more sense
• it is easier to write simulators for a core like that (<-- main reason why I've discovered this at all).

In other words I would move those two CSRs to Non-standard read/write and Non-standard read only areas respectively.

I already wrote to Charles Papon (author of VexRiscv) about this but I think it makes sense to point it out here as well as this will have to be updated both in VexRiscv plugin and in the LiteX code.

Installation error on CentOS 6.9 with Python 3.4

When I typed following command to install Litex:

sudo python3 setup.py install

Some errors propmted and It seems some packages were still using python 2 syntax ?

 File "/usr/lib/python3.4/site-packages/litex-0.1-py3.4.egg/litex/build/sim/core/modules/ethernet/tapcfg/drivers/osx/tuntap/test/tuntap/interface_harness.py", line 231
    return filter(lambda (a, n, d): a != None,
                         ^
SyntaxError: invalid syntax

  File "/usr/lib/python3.4/site-packages/litex-0.1-py3.4.egg/litex/build/sim/core/modules/ethernet/tapcfg/drivers/osx/tuntap/test/tuntap/route.py", line 85
    def add_addr((addr_flags, payload), (addr, flag)):
                 ^
SyntaxError: invalid syntax

  File "/usr/lib/python3.4/site-packages/litex-0.1-py3.4.egg/litex/build/sim/core/modules/ethernet/tapcfg/scons-tools/crossmingw.py", line 88
    raise SCons.Errors.UserError, "A shared library should have exactly one target with the suffix: %s" % env.subst("$SHLIBSUFFIX")
...

BIOS breaks without DDR main ram

This use to build fine on older versions of LiteX / LiteDRAM.

make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/basys3_base_lm32/software/libnet'
make[1]: Entering directory `/home/travis/build/mithro/litex-buildenv/build/basys3_base_lm32/software/bios'
make[1]: warning: jobserver unavailable: using -j1.  Add `+' to parent make rule.
 CC       isr.o
 CC       sdram.o
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c: In function 'memtest_bus':
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c:544:49: error: 'MAIN_RAM_BASE' undeclared (first use in this function); did you mean 'SRAM_BASE'?
  volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
                                                 ^~~~~~~~~~~~~
                                                 SRAM_BASE
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c:544:49: note: each undeclared identifier is reported only once for each function it appears in
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c: In function 'memtest_data':
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c:596:49: error: 'MAIN_RAM_BASE' undeclared (first use in this function); did you mean 'SRAM_BASE'?
  volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
                                                 ^~~~~~~~~~~~~
                                                 SRAM_BASE
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c: In function 'memtest_addr':
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c:636:49: error: 'MAIN_RAM_BASE' undeclared (first use in this function); did you mean 'SRAM_BASE'?
  volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
                                                 ^~~~~~~~~~~~~
                                                 SRAM_BASE
At top level:
/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/sdram.c:15:13: warning: 'cdelay' defined but not used [-Wunused-function]
 static void cdelay(int i)
             ^~~~~~
make[1]: *** [sdram.o] Error 1
make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/basys3_base_lm32/software/bios'
Traceback (most recent call last):
  File "./make.py", line 164, in <module>
    main()
  File "./make.py", line 148, in main
    vns = builder.build(**dict(args.build_option))
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 157, in build
    self._generate_software(not self.soc.integrated_rom_initialized)
  File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 142, in _generate_software
    subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
  File "/home/travis/build/mithro/litex-buildenv/build/conda/lib/python3.6/subprocess.py", line 291, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', '/home/travis/build/mithro/litex-buildenv/build/basys3_base_lm32/software/bios', '-f', '/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/software/bios/Makefile']' returned non-zero exit status 2.

Package installs 'test' package

I'm writing an ebuild for Pentoo (Gentoo) and facing an issue similar to the ypid/yaml4rst#1:

/usr/bin/python3.5 -O /var/tmp/portage/sys-apps/litex-20180531/temp/tmphmwkkika.py
removing /var/tmp/portage/sys-apps/litex-20180531/temp/tmphmwkkika.py
writing byte-compilation script '/var/tmp/portage/sys-apps/litex-20180531/temp/tmptgofa80_.py'
/usr/bin/python3.5 -OO /var/tmp/portage/sys-apps/litex-20180531/temp/tmptgofa80_.py
removing /var/tmp/portage/sys-apps/litex-20180531/temp/tmptgofa80_.py
running install_egg_info
Copying litex.egg-info to /var/tmp/portage/sys-apps/litex-20180531/image/_python3.5/usr/lib64/python3.5/site-packages/litex-0.2.dev0-py3.5.egg-info
running install_scripts
Installing mkmscimg script to /var/tmp/portage/sys-apps/litex-20180531/image/_python3.5/usr/lib/python-exec/python3.5
Installing litex_term script to /var/tmp/portage/sys-apps/litex-20180531/image/_python3.5/usr/lib/python-exec/python3.5
Installing litex_server script to /var/tmp/portage/sys-apps/litex-20180531/image/_python3.5/usr/lib/python-exec/python3.5
 * ERROR: sys-apps/litex-20180531::pentoo failed (install phase):
 *   Package installs 'test' package which is forbidden and likely a bug in the build system.
 * 
 * Call stack:
 *     ebuild.sh, line  124:  Called src_install
 *   environment, line 2604:  Called distutils-r1_src_install
 *   environment, line  835:  Called _distutils-r1_run_foreach_impl 'distutils-r1_python_install'
 *   environment, line  334:  Called python_foreach_impl 'distutils-r1_run_phase' 'distutils-r1_python_install'
 *   environment, line 2151:  Called multibuild_foreach_variant '_python_multibuild_wrapper' 'distutils-r1_run_phase' 'distutils-r1_python_install'
 *   environment, line 1526:  Called _multibuild_run '_python_multibuild_wrapper' 'distutils-r1_run_phase' 'distutils-r1_python_install'
 *   environment, line 1524:  Called _python_multibuild_wrapper 'distutils-r1_run_phase' 'distutils-r1_python_install'
 *   environment, line  546:  Called distutils-r1_run_phase 'distutils-r1_python_install'
 *   environment, line  803:  Called distutils-r1_python_install
 *   environment, line  725:  Called die
 * The specific snippet of code:
 *               die "Package installs '${p}' package which is forbidden and likely a bug in the build system.";
 * 
 * If you need support, post the output of `emerge --info '=sys-apps/litex-20180531::pentoo'`,
 * the complete build log and the output of `emerge -pqv '=sys-apps/litex-20180531::pentoo'`.
 * The complete build log is located at '/var/tmp/portage/sys-apps/litex-20180531/temp/build.log'.
 * The ebuild environment file is located at '/var/tmp/portage/sys-apps/litex-20180531/temp/environment'.
 * Working directory: '/var/tmp/portage/sys-apps/litex-20180531/work/litex-c534250c43791612da2a03c1c93f992115d11f8c'
 * S: '/var/tmp/portage/sys-apps/litex-20180531/work/litex-c534250c43791612da2a03c1c93f992115d11f8c'

Could you help to fix it please?

Possible problem with DCACHE when using VexRiscv

I am using VexRiscv version of LiteX on Arty board.
I've discovered that any software running from DDR (from 0x40000000) via uploading a binary using flterm will after executing a few instructions crash in an exception with mbadaddr pointing to the place where it got stuck (usually 0x40000120) with mcause == 2 (unknown instruction).
This can be fixed (at least seems so) by cleaning DCACHE three times (no less, otherwise it will crash but somewhere further in the way):

diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 9e5a4dc..bf6c698 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -26,6 +26,9 @@ static void __attribute__((noreturn)) boot(unsigned int r1, unsigned int r2, uns
 	irq_setmask(0);
 	irq_setie(0);
 	flush_cpu_icache();
+	flush_cpu_dcache();
+	flush_cpu_dcache();
+	flush_cpu_dcache();
 	boot_helper(r1, r2, r3, addr);
 	while(1);
 }

Since this is a generic part of LiteX I assume this has to be a bug in VexRiscv cache handling (or I am completely misunderstanding something).

The way I generate the core is:

python3 litex/boards/targets/arty.py --cpu-type vexriscv --csr-csv csr.csv

minerva.core package not found

I just fetched the latest commits and I get this error on trying to compile:

Traceback (most recent call last):
File "/home/bunnie/code/netv2-merge/netv2mvp.py", line 25, in
from litex.soc.integration.soc_sdram import *
File "/home/bunnie/code/netv2-merge/deps/litex/litex/soc/integration/init.py", line 1, in
from litex.soc.integration.soc_core import SoCCore
File "/home/bunnie/code/netv2-merge/deps/litex/litex/soc/integration/soc_core.py", line 7, in
from litex.soc.cores.cpu import lm32, mor1kx, picorv32, vexriscv, minerva
File "/home/bunnie/code/netv2-merge/deps/litex/litex/soc/cores/cpu/minerva/init.py", line 1, in
from litex.soc.cores.cpu.minerva.core import Minerva
File "/home/bunnie/code/netv2-merge/deps/litex/litex/soc/cores/cpu/minerva/core.py", line 7, in
from litex.soc.cores.cpu.minerva.core import Minerva as MinervaCPU
ImportError: cannot import name 'Minerva'

Where do I grab the minerva package from?

migen.build and litex.build has differences for DDRInput

This seems possibly important?

--- third_party/litex/litex/build/xilinx/common.py      2018-10-03 15:56:19.937855898 -0700
+++ third_party/migen/migen/build/xilinx/common.py      2018-10-03 15:46:47.376587690 -0700
@@ -14,7 +14,7 @@
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.io import *
 
-from litex.build import tools
+from migen.build import tools
 
 
 colors = []
@@ -169,9 +169,9 @@
 class XilinxDDRInputImplS7(Module):
     def __init__(self, i, o1, o2, clk):
         self.specials += Instance("IDDR",
-                p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
+                p_DDR_CLK_EDGE="SAME_EDGE",
                 i_C=clk, i_CE=1, i_S=0, i_R=0,
-                o_D=i, i_Q1=o1, i_Q2=o2,
+                i_D=i, o_Q1=o1, o_Q2=o2,
         )
 
 
@@ -206,9 +206,10 @@
         self.specials += Instance("IDDRE1",
             p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
             p_IS_C_INVERTED=0,
+            p_IS_CB_INVERTED=1,
             i_D=i,
             o_Q1=o1, o_Q2=o2,
-            i_C=clk, i_CB=~clk,
+            i_C=clk, i_CB=clk,
             i_R=0
         )

picorv32 doesn't check (nor use) the "variant" argument.

Was looking at that "variants" the picorv32 supported and found out it is not checking (or using) the variant CPU config at all.

See

litex/litex/soc/cores/cpu/picorv32/core.py

Line 15 in a44181e

def __init__(self, platform, progaddr_reset, variant):

RISC-V: verify that BIOS' CRC is correct with risc32 toolchain

trellis builder needs to take package type as well

The Lattice trellis builder needs to take in the package type as well. I'll see if I can't create a pull request for this.

Problem with fpga 101 lesson/lab003

A months ago, I didn't have this problem. But i update litex and when i try to execute python3 base.py I get this:

Traceback (most recent call last):
  File "base.py", line 6, in <module>
    from litex.soc.integration.soc_core import *
  File "/usr/local/lib/python3.5/dist-packages/litex-0.2.dev0-py3.5.egg/litex/soc/integration/__init__.py", line 2, in <module>
    from litex.soc.integration.soc_sdram import SoCSDRAM
  File "/usr/local/lib/python3.5/dist-packages/litex-0.2.dev0-py3.5.egg/litex/soc/integration/soc_sdram.py", line 8, in <module>
    from litedram.frontend import crossbar
ImportError: cannot import name 'crossbar'

https://github.com/enjoy-digital/fpga_101/tree/master/lab003

Print git commit at bios startup

Right now bios prints:
(BIOS built on "__DATE__" "__TIME__"\n")

I'd good to extend this with git commit hash info.

Minerva CPU support

I was trying to build LiteX BIOS for Minerva CPU and noticed a strange thing:

There is a minerva-specific code in

litex/litex/soc/software/include/base/irq.h

Line 111 in 8f37730

asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));

, but it looks like a copy-paste from VexRiscv.

This file contains defines, but the values are VexRiscv-specific.

Here I can see that minerva supports both standard RISC-V CSRs (mie, mip, mstatus) and some "µarch specific": IRQ_MASK and IRQ_PENDING that looks similar to those from VexRiscv, but their values are different.

What is the status of Minerva support? Is this supposed to work?

Vexriscv-Debug missing

With 4225c3b the Vexriscv-Debug.v file is missing. This file was added back in as part of e8a30b95b9aa1445b5a4a76579a98a0552e2db53. The vexriscv submodule should be updated to at least this new commit.

litex has circular dependencies

• litex depends on litedram
• litedram depends on litex

See below;

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "litex/test_sim/conda/lib/python3.5/site-packages/litex-0.1+25.g868bc5d-py3.5.egg/litex/boards/targets/sim.py", line 10, in <module>
    from litex.soc.integration.soc_sdram import *
  File "litex/test_sim/conda/lib/python3.5/site-packages/litex-0.1+25.g868bc5d-py3.5.egg/litex/soc/integration/__init__.py", line 2, in <module>
    from litex.soc.integration.soc_sdram import SoCSDRAM
  File "litex/test_sim/conda/lib/python3.5/site-packages/litex-0.1+25.g868bc5d-py3.5.egg/litex/soc/integration/soc_sdram.py", line 8, in <module>
    from litedram.frontend import crossbar
ImportError: No module named 'litedram'

Duplicate constraint raises wrong exception

At https://github.com/enjoy-digital/litex/blob/master/litex/build/xilinx/vivado.py#L254 it raises ValueError if a constraint exists. I think it should raise ConstraintError so I can be caught at https://github.com/enjoy-digital/litex/blob/master/litex/build/generic_platform.py#L314

I'm still feeling my way around litex so perhaps I'm missing something here.

File "/home/tom/git/im-tomu/foboot/hw/deps/litex/litex/build/xilinx/platform.py", line 48, in add_period_constraint
self.toolchain.add_period_constraint(self, clk, period)
File "/home/tom/git/im-tomu/foboot/hw/deps/litex/litex/build/xilinx/vivado.py", line 254, in add_period_constraint
raise ValueError("A period constraint already exists")
ValueError: A period constraint already exists

Support multiple period constraits with nextpnr

Right now, nextpnr will pick the highest frequency and try to make all clock domains work at that frequency.

nextpnr supports varying clock domains by passing a python program in a file specified by --pre-pack.

This is documented at https://github.com/YosysHQ/nextpnr/blob/master/docs/constraints.md#clock-constraints

This is accomplished in migen already: https://github.com/m-labs/migen/blob/master/migen/build/lattice/icestorm.py#L28

Should migen.build replace litex.build?

It seems that we have both a litex.build and a migen.build now. Should we be trying to merge them?

Enable link time optimisation in builds

Link time optimisation seems to be resulting in much smaller binaries as any unused elements can be totally removed.

There are however some issues to make this work;

• Have to use a modern gcc
• Use GCC for linking
• Have to mark a couple of functions like the ISR as actually used.
• Have to link against libgcc

libbase in litex is missing vprintf

vprintf is needed to be able to wrap printf calls.

Allow litex_server to bind to other interfaces

The litex_server binary is incredibly useful for bridging Wishbone to Ethernet. It is some of the magic that makes Litex work.

I'm running litex_server on a Raspberry Pi, and I would like to run openocd and/or devmem2_litex on my development system. This requires that I bind litex_server to "0.0.0.0" instead of to "localhost".

Right now I manually modify litex_server, however this change is unsuitable for upstreaming because it is insecure.

It would be nice if there was a way to add an option (command-line switch, environment variable, or something else) to litex_server to enable this functionality.

Integrate more RISC-V cores and compare resources/max freq of all cores.

PicoRV32, VexRiscv are already supported, good candidates SRC1 (Syntacore) / RISCY (Pulp).

LiteX and Migen relationship and compatibility is unclear

Hi, I'm trying to wrap my head around the LiteX/Migen world because I want to get LiteScope running on my Lattice HX8K board. However, this is unfortunately turning out to be a rather frustrating experience.

On https://github.com/enjoy-digital/litex, it says "All Migen's platforms can also be used in LiteX" - which makes sense as https://www.bunniestudios.com/blog/?p=5018 mentions that "LiteX is a soft-fork of Migen/MiSoC". However, it is unclear to me why LiteX was created (instead of improving on Migen) and what the differences are. I would appreciate if those points were clarified in readme.md.

Anyway, I'd like to use https://github.com/m-labs/migen/blob/master/migen/build/platforms/ice40_hx8k_b_evn.py but when I specify it as a platform to LiteX, it complains that it doesn't know about it - which makes sense because litex and migen use different python name spaces. So how, then, can Migen platforms be used in LiteX? As a newbie, I'm not sure how this can be achieved and would appreciate a more precise expression such as "All of Migen's platforms can also be used in LiteX with minor modifications" - or an explanation of how to use the platforms that only Migen currently supports.

Thanks for your hard work!

Installing with pip does not include submodules

When installing litex with pip install git+https://github.com/enjoy-digital/litex, it does not clone submodules (e.g. litex/soc/cores/cpu/vexriscv/verilog/).

Presumably, pip can handle submodules.

Import the Taiga high performance RISC-V core

Taiga is a 32-bit RISC-V processor designed for running Linux and SMP type things on FPGAs. Taiga is licensed under the Apache License, Version 2.0

Currently the only Linux supporting RISC-V processor we have is VexRISCV. It would be good to have a second RISC-V processor which targets high performance and Linux.

See the following description;

Taiga is a 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide and Atomic extensions (RV32IMA). The processor is written in SystemVerilog and has been designed to be both highly extensible and highly configurable.
The pipeline has been designed to support parallel, variable-latency execution units and to readily support the inclusion of new execution units.

cpu_interface: select_triple silently returns None

Related to this change here:
b528a00

Instead of a useful error message compilation fails with:
File "core_nopll.py", line 247, in
main()
File "core_nopll.py", line 226, in main
vns = builder.build(build_name="litedram_core", regular_comb=False)
File "/home/john/repos/litex/litex/soc/integration/builder.py", line 156, in build
self._generate_includes()
File "/home/john/repos/litex/litex/soc/integration/builder.py", line 72, in _generate_includes
define(k, v)
File "/home/john/repos/litex/litex/soc/integration/builder.py", line 70, in define
variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
File "/home/john/repos/litex/litex/soc/integration/builder.py", line 27, in _makefile_escape
return s.replace("\", "\\")
AttributeError: 'NoneType' object has no attribute 'replace'

CSR constants should contain more information about platform / architecture...

It would be good to have things like PLATFORM and TARGET values in them.

Support patching ICE40 SRAM images

The ICE40 toolchain has the ability to patch block ram in the emitted bitstream. However, because it uses heuristics to locate the memory, it requires that the ram contain random data.

It is possible to hack litex to generate a ROM image that fills the entire area with random data:

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 09de869..a9fee3f 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -279,6 +279,10 @@ class SoCCore(Module):
         self.cpu_or_bridge = self.cpu

     def initialize_rom(self, data):
+        import random
+        data = []
+        for d in range(self.rom.mem.depth):
+            data.append(random.getrandbits(32))
         self.rom.mem.init = data

     def add_wb_master(self, wbm):

We can then patch the emitted rom file with the actual contents of bios.bin.

There are a few issues:

1. migen does not emit zero-padded memory files, so we must pad them before we hand them to icebram
2. the bios.bin file must be converted to 32-bit hex values and padded to fill the entire memory
3. memory values may need to be byteswapped.

I'm not very good with python, so I hacked together a C program and shell script combination that fixes up mem.init and patches it with the contents of bios.bin.

C program:

#include <stdio.h>
#include <stdlib.h>
#include <sys/stat.h>
#include <unistd.h>
#include <fcntl.h>
#include <stdint.h>
#include <string.h>
#include <errno.h>

#define SWAP_BYTES // Define for lm32, undefine for riscv

static int rom_to_hex(const char *src, const char *dst, uint32_t mem_size) {
    FILE *outfile;
    char bfr[4];
    uint32_t file_size = 0;

    int fd = open(src, O_RDONLY);
    if (fd == -1) {
        fprintf(stderr, "unable to open src rom file %s: %s\n", src, strerror(errno));
        return 1;
    }

    outfile = fopen(dst, "w");
    if (!outfile) {
        fprintf(stderr, "unable to open dest rom file %s: %s\n", dst, strerror(errno));
        return 1;
    }

    while (read(fd, bfr, 4) == 4) {
#ifdef SWAP_BYTES
        fprintf(outfile, "%02x%02x%02x%02x\n", 0xff & bfr[0], 0xff & bfr[1], 0xff & bfr[2], 0xff & bfr[3]);
#else
        fprintf(outfile, "%02x%02x%02x%02x\n", 0xff & bfr[3], 0xff & bfr[2], 0xff & bfr[1], 0xff & bfr[0]);
#endif
        file_size += 4;
    }

    memset(bfr, 0, sizeof(bfr));
    while (file_size < mem_size) {
        fprintf(outfile, "%02x%02x%02x%02x\n", 0xff & bfr[3], 0xff & bfr[2], 0xff & bfr[1], 0xff & bfr[0]);
        file_size += 4;
    }
    fclose(outfile);

    return 0;
}

static int patchup_mem(const char *src, const char *dst, uint32_t *mem_size) {
    *mem_size = 0;
    FILE *s = fopen(src, "r");
    if (!s) {
        fprintf(stderr, "unable to open source mem file %s: %s\n", src, strerror(errno));
        return 1;
    }

    FILE *d = fopen(dst, "w");
    if (!d) {
        fprintf(stderr, "unable to open dest mem file %s: %s\n", dst, strerror(errno));
        return 2;
    }

    char tmpline[128];
    while (fgets(tmpline, sizeof(tmpline)-1, s) != NULL) {
        uint32_t word = strtoul(tmpline, NULL, 16);
        fprintf(d, "%08x\n", word);
        *mem_size += 4;
    }

    fclose(d);
    fclose(s);
    return 0;
}

int main(int argc, char **argv) {
    uint32_t mem_size;
    if (argc != 5) {
        printf("Usage: %s [src-mem] [dst-mem] [src-bin] [dst-bin]\n", argv[0]);
        return 1;
    }
    if (patchup_mem(argv[1], argv[2], &mem_size))
        return 1;
    if (rom_to_hex(argv[3], argv[4], mem_size))
        return 1;
    return 0;
}

Shell script:

#!/bin/sh
set -e
builddir=../build/fomu_evt_usb_lm32.minimal
src_bs=${builddir}/gateware/top.bin
src_mem=${builddir}/gateware/mem.init
dst_bs=patched.bin
dst_mem=${builddir}/software/bios/bios.bin

iceunpack < "${src_bs}" > top.asc
./repack "${src_mem}" top.hex "${dst_mem}" patched.hex
icebram top.hex patched.hex < top.asc | icepack > "${dst_bs}"

echo "Patched file generated: ${dst_bs}"

litex_server seems to be broken

https://travis-ci.org/mithro/litex

The command "litex_server --help" exited with 0.
0.16s$ litex_client --help || true
Traceback (most recent call last):
  File "/home/travis/virtualenv/python3.3.5/lib/python3.3/site-packages/pkg_resources/__init__.py", line 2318, in resolve
    return functools.reduce(getattr, self.attrs, module)
AttributeError: 'module' object has no attribute 'main'
During handling of the above exception, another exception occurred:
Traceback (most recent call last):
  File "/home/travis/virtualenv/python3.3.5/bin/litex_client", line 9, in <module>
    load_entry_point('litex==0.1+37.g512098f', 'console_scripts', 'litex_client')()
  File "/home/travis/virtualenv/python3.3.5/lib/python3.3/site-packages/pkg_resources/__init__.py", line 519, in load_entry_point
    return get_distribution(dist).load_entry_point(group, name)
  File "/home/travis/virtualenv/python3.3.5/lib/python3.3/site-packages/pkg_resources/__init__.py", line 2630, in load_entry_point
    return ep.load()
  File "/home/travis/virtualenv/python3.3.5/lib/python3.3/site-packages/pkg_resources/__init__.py", line 2310, in load
    return self.resolve()
  File "/home/travis/virtualenv/python3.3.5/lib/python3.3/site-packages/pkg_resources/__init__.py", line 2320, in resolve
    raise ImportError(str(exc))
ImportError: 'module' object has no attribute 'main'

Manually exiting litex_term breaks shell

When exiting litex_term with ctrl-c the terminal gets corrupted until reset is run which fixes the terminal again. Or am I just missing some proper mechanism to exit litex_term? When unplugging the board, litex_term exits without breaking the shell.

regression: memtest fails on nexys4ddr SoC startup

I'm using the script below to build a vexriscv variant of litex/boards/targets/nexys4ddr.py, and it works with commit dad7b29, but breaks with "Memtest bus failed 128/256 errors, Memtest data failed: 524288/524288 errors" if I build the current master (2ebfab5). Here's my build script:

rm -rf ~/.local/bin ~/.local/lib ~/LITEX
mkdir ~/LITEX; cd ~/LITEX
# grab litex & friends (only litex has submodules, but --recursive won't hurt):
PRJ='x dram eth usb pcie sdcard iclink video scope'
for i in $PRJ; do
  git clone --recursive https://github.com/enjoy-digital/lite$i
done

# FIXME: Memtest fails, this rollback fixes it:
(cd litex;    git checkout dad7b292)

# "install" to local user's ~/.local/[usr|bin]:
for i in $PRJ; do
  (cd lite$i; python3 setup.py develop --user)
done

# build nexys4ddr full SoC example (using vexriscv cpu, and custom vivado path):
sed -i '/^\( *\)integrated_sram_size.*$/s//&\n\1cpu_type="vexriscv",/' \
  litex/litex/boards/targets/nexys4ddr.py
sed -i '/builder.build/s|()|(toolchain_path="/home/somlo/Xilinx/Vivado")|' \
  litex/litex/boards/targets/nexys4ddr.py
litex/litex/boards/targets/nexys4ddr.py

EDIT: after a bisect, the culprit appears to be commit 3dd529e ("add ECP5 support") -- something about the modified #defines in sdram.c disagrees with the proper operation of the nexys4ddr DDR2 controller.

lm32 broken on default config with Xilinx ISE

https://travis-ci.org/timvideos/litex-buildenv/jobs/469312838

Error detected! - ERROR:HDLCompiler:281 - "/home/travis/build/timvideos/litex-buildenv/third_party/litex/litex/soc/cores/cpu/lm32/verilog/submodule/rtl/lm32_include.v" Line 61: Cannot open include file "lm32_config.v".

Land linux optimized version of vexriscv

@antmicro is working on 32bit Linux on RISCV. It would be good to have the vexriscv variant which supports linux in the same way there is a or1k variant which supports linux.

TFTP transfer bug

I was experiencing strange TFTP transfer issues. I diagnosed it in the chainloader I am working on (where I made a copy of the tftp/udp code). The culprit was documented here:
https://github.com/tweakoz/litex-chainloader/blob/master/tftp.cpp#L136
I would submit a fix and pull request, but I would not have time to test all scenarios, atm...
The fix seemed to work on my chainloader - so the same approach might work here...

Option to change toolchain path?

I'm trying to build Arty-SoC but I'm getting an error that the Xilinx tools were not found in /opt/Xilinx/Vivado which makes sense because I installed it at $HOME/Software/Xilinx/Vivado. Other than changing the hardcoded path, is there a way to point to a different toolchain path on the command line as an argument?

PEP8 issues

Here is the current list of PEP8 errors in litex

running pep8
./setup.py:13:1: E302 expected 2 blank lines, found 1
./setuptools_pep8-0.9.0-py3.4.egg/tests/test_pep8_command.py:24:80: E501 line too long (116 > 79 characters)
./setuptools_pep8-0.9.0-py3.4.egg/setuptools_pep8/setuptools_command.py:16:80: E501 line too long (111 > 79 characters)
./litex/build/generic_programmer.py:30:1: W391 blank line at end of file
./litex/build/sim/platform.py:16:80: E501 line too long (87 > 79 characters)
./litex/build/sim/platform.py:20:1: W391 blank line at end of file
./litex/build/sim/verilator.py:1:80: E501 line too long (83 > 79 characters)
./litex/build/sim/verilator.py:42:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:43:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:44:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:46:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:47:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:48:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:49:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:63:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:64:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:65:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:67:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:68:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:69:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:70:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:83:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:84:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:85:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:86:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:87:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:88:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:89:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:113:80: E501 line too long (104 > 79 characters)
./litex/build/sim/verilator.py:117:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:118:5: E122 continuation line missing indentation or outdented
./litex/build/sim/verilator.py:120:80: E501 line too long (82 > 79 characters)
./litex/build/sim/verilator.py:123:80: E501 line too long (103 > 79 characters)
./litex/build/sim/verilator.py:131:80: E501 line too long (102 > 79 characters)
./litex/build/sim/verilator.py:148:13: E128 continuation line under-indented for visual indent
./litex/build/sim/verilator.py:166:80: E501 line too long (85 > 79 characters)
./litex/build/lattice/common.py:12:17: E128 continuation line under-indented for visual indent
./litex/build/lattice/common.py:14:17: E128 continuation line under-indented for visual indent
./litex/build/lattice/common.py:27:17: E128 continuation line under-indented for visual indent
./litex/build/lattice/common.py:28:17: E128 continuation line under-indented for visual indent
./litex/build/lattice/common.py:29:17: E128 continuation line under-indented for visual indent
./litex/build/lattice/common.py:30:9: E124 closing bracket does not match visual indentation
./litex/build/lattice/diamond.py:49:80: E501 line too long (130 > 79 characters)
./litex/build/lattice/diamond.py:69:80: E501 line too long (108 > 79 characters)
./litex/build/lattice/diamond.py:93:80: E501 line too long (90 > 79 characters)
./litex/build/lattice/diamond.py:95:80: E501 line too long (80 > 79 characters)
./litex/build/lattice/diamond.py:106:80: E501 line too long (140 > 79 characters)
./litex/build/lattice/platform.py:18:80: E501 line too long (87 > 79 characters)
./litex/build/lattice/programmer.py:8:80: E501 line too long (94 > 79 characters)
./litex/build/xilinx/__init__.py:2:80: E501 line too long (86 > 79 characters)
./litex/build/xilinx/common.py:21:27: W503 line break before binary operator
./litex/build/xilinx/common.py:47:13: E261 at least two spaces before inline comment
./litex/build/xilinx/common.py:58:80: E501 line too long (95 > 79 characters)
./litex/build/xilinx/common.py:83:80: E501 line too long (89 > 79 characters)
./litex/build/xilinx/common.py:84:13: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:98:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:100:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:135:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:136:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:137:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:138:9: E124 closing bracket does not match visual indentation
./litex/build/xilinx/common.py:170:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:171:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:172:17: E128 continuation line under-indented for visual indent
./litex/build/xilinx/common.py:173:9: E124 closing bracket does not match visual indentation
./litex/build/xilinx/ise.py:31:80: E501 line too long (81 > 79 characters)
./litex/build/xilinx/ise.py:85:9: E128 continuation line under-indented for visual indent
./litex/build/xilinx/ise.py:106:80: E501 line too long (80 > 79 characters)
./litex/build/xilinx/ise.py:112:13: E128 continuation line under-indented for visual indent
./litex/build/xilinx/ise.py:113:13: E128 continuation line under-indented for visual indent
./litex/build/xilinx/ise.py:116:80: E501 line too long (83 > 79 characters)
./litex/build/xilinx/ise.py:136:13: E128 continuation line under-indented for visual indent
./litex/build/xilinx/ise.py:158:80: E501 line too long (84 > 79 characters)
./litex/build/xilinx/ise.py:165:80: E501 line too long (120 > 79 characters)
./litex/build/xilinx/ise.py:168:80: E501 line too long (100 > 79 characters)
./litex/build/xilinx/ise.py:172:80: E501 line too long (84 > 79 characters)
./litex/build/xilinx/platform.py:26:80: E501 line too long (87 > 79 characters)
./litex/build/xilinx/programmer.py:21:80: E501 line too long (125 > 79 characters)
./litex/build/xilinx/programmer.py:25:1: E303 too many blank lines (3)
./litex/build/xilinx/programmer.py:39:20: E128 continuation line under-indented for visual indent
./litex/build/xilinx/programmer.py:43:80: E501 line too long (89 > 79 characters)
./litex/build/xilinx/programmer.py:81:80: E501 line too long (84 > 79 characters)
./litex/build/xilinx/programmer.py:88:5: E301 expected 1 blank line, found 0
./litex/build/xilinx/programmer.py:98:80: E501 line too long (81 > 79 characters)
./litex/build/xilinx/programmer.py:114:80: E501 line too long (81 > 79 characters)
./litex/build/xilinx/programmer.py:115:80: E501 line too long (112 > 79 characters)
./litex/build/xilinx/programmer.py:117:80: E501 line too long (98 > 79 characters)
./litex/build/xilinx/programmer.py:118:80: E501 line too long (92 > 79 characters)
./litex/build/xilinx/programmer.py:119:80: E501 line too long (98 > 79 characters)
./litex/build/xilinx/programmer.py:120:80: E501 line too long (93 > 79 characters)
./litex/build/xilinx/programmer.py:123:80: E501 line too long (111 > 79 characters)
./litex/build/xilinx/programmer.py:124:80: E501 line too long (105 > 79 characters)
./litex/build/xilinx/programmer.py:125:80: E501 line too long (120 > 79 characters)
./litex/build/xilinx/programmer.py:126:80: E501 line too long (98 > 79 characters)
./litex/build/xilinx/programmer.py:127:80: E501 line too long (92 > 79 characters)
./litex/build/xilinx/programmer.py:128:80: E501 line too long (98 > 79 characters)
./litex/build/xilinx/programmer.py:129:80: E501 line too long (93 > 79 characters)
./litex/build/xilinx/programmer.py:132:80: E501 line too long (389 > 79 characters)
./litex/build/xilinx/programmer.py:133:80: E501 line too long (90 > 79 characters)
./litex/build/xilinx/vivado.py:43:80: E501 line too long (85 > 79 characters)
./litex/build/xilinx/vivado.py:56:80: E501 line too long (86 > 79 characters)
./litex/build/xilinx/vivado.py:64:80: E501 line too long (86 > 79 characters)
./litex/build/xilinx/vivado.py:89:80: E501 line too long (88 > 79 characters)
./litex/build/xilinx/vivado.py:90:80: E501 line too long (150 > 79 characters)
./litex/build/xilinx/vivado.py:91:80: E501 line too long (117 > 79 characters)
./litex/build/xilinx/vivado.py:92:80: E501 line too long (90 > 79 characters)
./litex/build/xilinx/vivado.py:96:80: E501 line too long (117 > 79 characters)
./litex/build/xilinx/vivado.py:97:80: E501 line too long (90 > 79 characters)
./litex/build/xilinx/vivado.py:99:80: E501 line too long (95 > 79 characters)
./litex/build/xilinx/vivado.py:100:80: E501 line too long (96 > 79 characters)
./litex/build/xilinx/vivado.py:102:80: E501 line too long (86 > 79 characters)
./litex/build/xilinx/vivado.py:104:80: E501 line too long (96 > 79 characters)
./litex/build/xilinx/vivado.py:115:13: E128 continuation line under-indented for visual indent
./litex/build/xilinx/vivado.py:115:80: E501 line too long (82 > 79 characters)
./litex/build/xilinx/vivado.py:129:80: E501 line too long (80 > 79 characters)
./litex/boards/targets/arty.py:16:1: E302 expected 2 blank lines, found 1
./litex/boards/targets/arty.py:47:22: E265 block comment should start with '# '
./litex/boards/targets/arty.py:51:22: E265 block comment should start with '# '
./litex/boards/targets/arty.py:55:22: E265 block comment should start with '# '
./litex/boards/targets/arty.py:56:13: E124 closing bracket does not match visual indentation
./litex/boards/targets/arty.py:63:9: E303 too many blank lines (2)
./litex/boards/targets/arty.py:104:80: E501 line too long (83 > 79 characters)
./litex/boards/targets/arty.py:106:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/arty.py:108:80: E501 line too long (91 > 79 characters)
./litex/boards/targets/arty.py:132:80: E501 line too long (84 > 79 characters)
./litex/boards/targets/de0nano.py:21:51: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:21:53: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:22:51: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:22:53: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:23:52: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:23:54: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:24:53: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:24:55: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:25:53: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:25:55: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:25:80: E501 line too long (85 > 79 characters)
./litex/boards/targets/de0nano.py:26:53: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:26:55: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:27:59: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:27:61: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:27:80: E501 line too long (81 > 79 characters)
./litex/boards/targets/de0nano.py:28:59: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:28:61: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:29:45: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:29:47: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:29:80: E501 line too long (87 > 79 characters)
./litex/boards/targets/de0nano.py:30:45: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:30:47: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:31:51: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:31:53: E251 unexpected spaces around keyword / parameter equals
./litex/boards/targets/de0nano.py:51:9: E124 closing bracket does not match visual indentation
./litex/boards/targets/de0nano.py:105:1: E302 expected 2 blank lines, found 1
./litex/boards/targets/de0nano.py:106:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/kc705.py:29:80: E501 line too long (87 > 79 characters)
./litex/boards/targets/kc705.py:48:80: E501 line too long (85 > 79 characters)
./litex/boards/targets/kc705.py:51:80: E501 line too long (82 > 79 characters)
./litex/boards/targets/kc705.py:54:80: E501 line too long (83 > 79 characters)
./litex/boards/targets/kc705.py:56:62: E261 at least two spaces before inline comment
./litex/boards/targets/kc705.py:56:63: E262 inline comment should start with '# '
./litex/boards/targets/kc705.py:58:62: E261 at least two spaces before inline comment
./litex/boards/targets/kc705.py:58:63: E262 inline comment should start with '# '
./litex/boards/targets/kc705.py:59:13: E124 closing bracket does not match visual indentation
./litex/boards/targets/kc705.py:72:13: E124 closing bracket does not match visual indentation
./litex/boards/targets/kc705.py:75:80: E501 line too long (95 > 79 characters)
./litex/boards/targets/kc705.py:96:80: E501 line too long (81 > 79 characters)
./litex/boards/targets/kc705.py:99:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/kc705.py:105:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/kc705.py:106:80: E501 line too long (111 > 79 characters)
./litex/boards/targets/kc705.py:107:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/kc705.py:134:80: E501 line too long (80 > 79 characters)
./litex/boards/targets/kc705.py:135:80: E501 line too long (97 > 79 characters)
./litex/boards/targets/kc705.py:136:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/kc705.py:138:80: E501 line too long (91 > 79 characters)
./litex/boards/targets/minispartan6.py:37:80: E501 line too long (88 > 79 characters)
./litex/boards/targets/minispartan6.py:38:80: E501 line too long (81 > 79 characters)
./litex/boards/targets/minispartan6.py:39:80: E501 line too long (101 > 79 characters)
./litex/boards/targets/minispartan6.py:40:80: E501 line too long (100 > 79 characters)
./litex/boards/targets/minispartan6.py:42:80: E501 line too long (87 > 79 characters)
./litex/boards/targets/minispartan6.py:43:80: E501 line too long (92 > 79 characters)
./litex/boards/targets/minispartan6.py:54:80: E501 line too long (86 > 79 characters)
./litex/boards/targets/minispartan6.py:55:80: E501 line too long (91 > 79 characters)
./litex/boards/targets/minispartan6.py:56:9: E124 closing bracket does not match visual indentation
./litex/boards/targets/minispartan6.py:87:80: E501 line too long (86 > 79 characters)
./litex/boards/targets/nexys_video.py:46:13: E124 closing bracket does not match visual indentation
./litex/boards/targets/nexys_video.py:58:13: E124 closing bracket does not match visual indentation
./litex/boards/targets/nexys_video.py:61:80: E501 line too long (95 > 79 characters)
./litex/boards/targets/nexys_video.py:96:80: E501 line too long (85 > 79 characters)
./litex/boards/targets/nexys_video.py:98:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/nexys_video.py:100:80: E501 line too long (91 > 79 characters)
./litex/boards/targets/nexys_video.py:102:1: E302 expected 2 blank lines, found 1
./litex/boards/targets/nexys_video.py:103:80: E501 line too long (81 > 79 characters)
./litex/boards/targets/nexys_video.py:123:80: E501 line too long (84 > 79 characters)
./litex/boards/targets/sim.py:22:1: E302 expected 2 blank lines, found 1
./litex/boards/targets/sim.py:26:13: E128 continuation line under-indented for visual indent
./litex/boards/targets/sim.py:32:80: E501 line too long (81 > 79 characters)
./litex/boards/targets/sim.py:79:80: E501 line too long (89 > 79 characters)
./litex/boards/targets/sim.py:81:80: E501 line too long (91 > 79 characters)
./litex/boards/targets/sim.py:85:1: E303 too many blank lines (3)
./litex/boards/targets/sim.py:86:80: E501 line too long (80 > 79 characters)
./litex/boards/targets/simple.py:15:1: E302 expected 2 blank lines, found 1
./litex/boards/targets/simple.py:18:13: E128 continuation line under-indented for visual indent
./litex/boards/targets/simple.py:19:13: E128 continuation line under-indented for visual indent
./litex/boards/targets/simple.py:20:13: E128 continuation line under-indented for visual indent
./litex/boards/targets/simple.py:21:13: E128 continuation line under-indented for visual indent
./litex/boards/targets/simple.py:51:80: E501 line too long (91 > 79 characters)
./litex/boards/platforms/arty.py:19:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/arty.py:44:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/arty.py:72:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/arty.py:78:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/arty.py:91:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/arty.py:108:80: E501 line too long (86 > 79 characters)
./litex/boards/platforms/de0nano.py:32:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:43:80: E501 line too long (81 > 79 characters)
./litex/boards/platforms/de0nano.py:46:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:54:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:60:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:66:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:74:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:78:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/de0nano.py:79:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/de0nano.py:81:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:84:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/de0nano.py:85:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/de0nano.py:87:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/de0nano.py:91:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:2:80: E501 line too long (81 > 79 characters)
./litex/boards/platforms/kc705.py:32:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:42:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:47:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:65:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:89:80: E501 line too long (104 > 79 characters)
./litex/boards/platforms/kc705.py:110:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/kc705.py:122:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/kc705.py:124:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/kc705.py:132:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:139:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:154:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:164:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:173:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:182:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:191:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:339:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:416:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/kc705.py:427:13: E128 continuation line under-indented for visual indent
./litex/boards/platforms/kc705.py:429:80: E501 line too long (108 > 79 characters)
./litex/boards/platforms/kc705.py:431:80: E501 line too long (113 > 79 characters)
./litex/boards/platforms/kc705.py:432:80: E501 line too long (170 > 79 characters)
./litex/boards/platforms/kc705.py:443:80: E501 line too long (81 > 79 characters)
./litex/boards/platforms/kc705.py:452:80: E501 line too long (81 > 79 characters)
./litex/boards/platforms/kc705.py:458:80: E501 line too long (92 > 79 characters)
./litex/boards/platforms/minispartan6.py:32:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:39:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:44:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:49:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:53:80: E501 line too long (84 > 79 characters)
./litex/boards/platforms/minispartan6.py:54:80: E501 line too long (92 > 79 characters)
./litex/boards/platforms/minispartan6.py:63:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:73:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:83:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:92:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:99:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/minispartan6.py:126:80: E501 line too long (81 > 79 characters)
./litex/boards/platforms/nexys_video.py:42:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/nexys_video.py:52:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/nexys_video.py:77:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/nexys_video.py:83:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/nexys_video.py:94:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/nexys_video.py:109:64: E261 at least two spaces before inline comment
./litex/boards/platforms/nexys_video.py:110:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/nexys_video.py:124:64: E261 at least two spaces before inline comment
./litex/boards/platforms/nexys_video.py:125:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/nexys_video.py:142:80: E501 line too long (86 > 79 characters)
./litex/boards/platforms/nexys_video.py:145:5: E303 too many blank lines (2)
./litex/boards/platforms/nexys_video.py:157:80: E501 line too long (81 > 79 characters)
./litex/boards/platforms/sim.py:20:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/sim.py:23:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/sim.py:32:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/sim.py:40:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/versa.py:34:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/versa.py:41:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/versa.py:54:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/versa.py:61:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/versa.py:74:5: E124 closing bracket does not match visual indentation
./litex/boards/platforms/versa.py:88:80: E501 line too long (84 > 79 characters)
./litex/boards/platforms/versa.py:92:80: E501 line too long (84 > 79 characters)
./litex/boards/platforms/versa.py:95:5: E301 expected 1 blank line, found 0
./litex/gen/sim/core.py:8:35: E128 continuation line under-indented for visual indent
./litex/gen/sim/core.py:9:35: E128 continuation line under-indented for visual indent
./litex/gen/sim/core.py:12:31: E128 continuation line under-indented for visual indent
./litex/gen/sim/core.py:151:80: E501 line too long (82 > 79 characters)
./litex/gen/sim/core.py:160:80: E501 line too long (81 > 79 characters)
./litex/gen/sim/core.py:223:80: E501 line too long (90 > 79 characters)
./litex/gen/sim/core.py:232:80: E501 line too long (83 > 79 characters)
./litex/gen/sim/core.py:243:80: E501 line too long (84 > 79 characters)
./litex/gen/sim/core.py:251:21: W503 line break before binary operator
./litex/gen/sim/vcd.py:65:17: W503 line break before binary operator
./litex/gen/fhdl/bitcontainer.py:104:11: E127 continuation line over-indented for visual indent
./litex/gen/fhdl/bitcontainer.py:105:15: E111 indentation is not a multiple of four
./litex/gen/fhdl/decorators.py:74:80: E501 line too long (119 > 79 characters)
./litex/gen/fhdl/decorators.py:79:17: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/module.py:64:80: E501 line too long (86 > 79 characters)
./litex/gen/fhdl/module.py:136:80: E501 line too long (100 > 79 characters)
./litex/gen/fhdl/module.py:141:80: E501 line too long (100 > 79 characters)
./litex/gen/fhdl/module.py:162:80: E501 line too long (82 > 79 characters)
./litex/gen/fhdl/module.py:168:80: E501 line too long (108 > 79 characters)
./litex/gen/fhdl/module.py:170:80: E501 line too long (114 > 79 characters)
./litex/gen/fhdl/module.py:175:80: E501 line too long (81 > 79 characters)
./litex/gen/fhdl/namer.py:31:80: E501 line too long (85 > 79 characters)
./litex/gen/fhdl/namer.py:69:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/namer.py:132:80: E501 line too long (105 > 79 characters)
./litex/gen/fhdl/namer.py:150:80: E501 line too long (86 > 79 characters)
./litex/gen/fhdl/namer.py:155:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/namer.py:199:80: E501 line too long (84 > 79 characters)
./litex/gen/fhdl/simplify.py:20:80: E501 line too long (121 > 79 characters)
./litex/gen/fhdl/simplify.py:29:80: E501 line too long (112 > 79 characters)
./litex/gen/fhdl/simplify.py:30:80: E501 line too long (116 > 79 characters)
./litex/gen/fhdl/simplify.py:34:80: E501 line too long (101 > 79 characters)
./litex/gen/fhdl/simplify.py:38:80: E501 line too long (128 > 79 characters)
./litex/gen/fhdl/simplify.py:39:80: E501 line too long (112 > 79 characters)
./litex/gen/fhdl/simplify.py:40:80: E501 line too long (128 > 79 characters)
./litex/gen/fhdl/simplify.py:98:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/simplify.py:99:26: E261 at least two spaces before inline comment
./litex/gen/fhdl/specials.py:12:5: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/specials.py:67:80: E501 line too long (81 > 79 characters)
./litex/gen/fhdl/specials.py:73:80: E501 line too long (82 > 79 characters)
./litex/gen/fhdl/specials.py:89:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/specials.py:91:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/specials.py:93:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/specials.py:95:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/specials.py:101:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/specials.py:104:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/specials.py:140:80: E501 line too long (94 > 79 characters)
./litex/gen/fhdl/specials.py:162:22: E701 multiple statements on one line (colon)
./litex/gen/fhdl/specials.py:176:80: E501 line too long (91 > 79 characters)
./litex/gen/fhdl/specials.py:188:7: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/specials.py:189:7: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/specials.py:237:7: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/specials.py:238:7: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/specials.py:257:11: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/specials.py:258:11: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/specials.py:265:9: E301 expected 1 blank line, found 0
./litex/gen/fhdl/specials.py:301:80: E501 line too long (119 > 79 characters)
./litex/gen/fhdl/specials.py:304:80: E501 line too long (100 > 79 characters)
./litex/gen/fhdl/specials.py:307:80: E501 line too long (86 > 79 characters)
./litex/gen/fhdl/specials.py:309:80: E501 line too long (105 > 79 characters)
./litex/gen/fhdl/specials.py:324:80: E501 line too long (98 > 79 characters)
./litex/gen/fhdl/specials.py:327:80: E501 line too long (112 > 79 characters)
./litex/gen/fhdl/specials.py:329:80: E501 line too long (93 > 79 characters)
./litex/gen/fhdl/specials.py:339:80: E501 line too long (82 > 79 characters)
./litex/gen/fhdl/specials.py:353:80: E501 line too long (87 > 79 characters)
./litex/gen/fhdl/specials.py:360:80: E501 line too long (84 > 79 characters)
./litex/gen/fhdl/structure.py:11:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:37:21: W503 line break before binary operator
./litex/gen/fhdl/structure.py:43:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:48:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:50:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:52:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:54:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:56:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:58:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:60:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:62:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:64:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:66:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:68:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:70:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:72:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:74:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:76:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:81:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:83:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:85:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:87:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:89:5: E301 expected 1 blank line, found 0
./litex/gen/fhdl/structure.py:314:80: E501 line too long (143 > 79 characters)
./litex/gen/fhdl/structure.py:328:80: E501 line too long (94 > 79 characters)
./litex/gen/fhdl/structure.py:336:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/structure.py:351:80: E501 line too long (97 > 79 characters)
./litex/gen/fhdl/structure.py:529:44: W291 trailing whitespace
./litex/gen/fhdl/structure.py:530:21: W503 line break before binary operator
./litex/gen/fhdl/structure.py:553:25: W503 line break before binary operator
./litex/gen/fhdl/structure.py:554:25: W503 line break before binary operator
./litex/gen/fhdl/structure.py:579:13: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/structure.py:582:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/structure.py:583:13: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/structure.py:649:80: E501 line too long (92 > 79 characters)
./litex/gen/fhdl/structure.py:689:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/structure.py:690:24: E701 multiple statements on one line (colon)
./litex/gen/fhdl/structure.py:691:24: E701 multiple statements on one line (colon)
./litex/gen/fhdl/structure.py:692:28: E701 multiple statements on one line (colon)
./litex/gen/fhdl/structure.py:693:33: E701 multiple statements on one line (colon)
./litex/gen/fhdl/structure.py:707:13: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/structure.py:708:13: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/structure.py:722:1: E302 expected 2 blank lines, found 1
./litex/gen/fhdl/tools.py:87:9: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/tools.py:170:80: E501 line too long (83 > 79 characters)
./litex/gen/fhdl/tools.py:181:80: E501 line too long (83 > 79 characters)
./litex/gen/fhdl/tools.py:203:17: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/tools.py:242:80: E501 line too long (89 > 79 characters)
./litex/gen/fhdl/tracer.py:24:80: E501 line too long (101 > 79 characters)
./litex/gen/fhdl/tracer.py:48:80: E501 line too long (84 > 79 characters)
./litex/gen/fhdl/verilog.py:30:53: E231 missing whitespace after ','
./litex/gen/fhdl/verilog.py:98:15: E111 indentation is not a multiple of four
./litex/gen/fhdl/verilog.py:110:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/verilog.py:112:80: E501 line too long (92 > 79 characters)
./litex/gen/fhdl/verilog.py:139:80: E501 line too long (102 > 79 characters)
./litex/gen/fhdl/verilog.py:153:80: E501 line too long (84 > 79 characters)
./litex/gen/fhdl/verilog.py:208:80: E501 line too long (95 > 79 characters)
./litex/gen/fhdl/verilog.py:246:80: E501 line too long (80 > 79 characters)
./litex/gen/fhdl/verilog.py:249:80: E501 line too long (95 > 79 characters)
./litex/gen/fhdl/verilog.py:253:80: E501 line too long (96 > 79 characters)
./litex/gen/fhdl/verilog.py:257:80: E501 line too long (92 > 79 characters)
./litex/gen/fhdl/verilog.py:267:80: E501 line too long (84 > 79 characters)
./litex/gen/fhdl/verilog.py:276:80: E501 line too long (92 > 79 characters)
./litex/gen/fhdl/verilog.py:278:80: E501 line too long (102 > 79 characters)
./litex/gen/fhdl/verilog.py:284:3: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:285:3: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:286:3: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:287:3: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:288:3: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:289:3: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:290:3: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:319:42: E502 the backslash is redundant between brackets
./litex/gen/fhdl/verilog.py:320:9: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:320:49: E502 the backslash is redundant between brackets
./litex/gen/fhdl/verilog.py:321:9: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/verilog.py:333:80: E501 line too long (96 > 79 characters)
./litex/gen/fhdl/visit.py:6:35: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/visit.py:200:13: E128 continuation line under-indented for visual indent
./litex/gen/fhdl/visit.py:205:13: E128 continuation line under-indented for visual indent
./litex/gen/genlib/cdc.py:133:13: E124 closing bracket does not match visual indentation
./litex/gen/genlib/coding.py:33:22: E227 missing whitespace around bitwise or shift operator
./litex/gen/genlib/coding.py:92:35: E227 missing whitespace around bitwise or shift operator
./litex/gen/genlib/divider.py:32:13: E124 closing bracket does not match visual indentation
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./litex/gen/genlib/divider.py:35:21: E124 closing bracket does not match visual indentation
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./litex/gen/genlib/divider.py:39:13: E124 closing bracket does not match visual indentation
./litex/gen/genlib/fifo.py:14:13: E128 continuation line under-indented for visual indent
./litex/gen/genlib/fifo.py:15:9: E124 closing bracket does not match visual indentation
./litex/gen/genlib/fifo.py:96:13: E124 closing bracket does not match visual indentation
./litex/gen/genlib/fifo.py:103:13: E128 continuation line under-indented for visual indent
./litex/gen/genlib/fifo.py:121:13: E124 closing bracket does not match visual indentation
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./litex/gen/genlib/fifo.py:147:13: E124 closing bracket does not match visual indentation
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./litex/gen/genlib/fifo.py:149:13: E124 closing bracket does not match visual indentation
./litex/gen/genlib/fifo.py:190:80: E501 line too long (80 > 79 characters)
./litex/gen/genlib/fifo.py:191:17: E128 continuation line under-indented for visual indent
./litex/gen/genlib/fifo.py:191:17: W503 line break before binary operator
./litex/gen/genlib/fifo.py:195:17: E128 continuation line under-indented for visual indent
./litex/gen/genlib/fifo.py:195:17: W503 line break before binary operator
./litex/gen/genlib/fifo.py:196:17: E122 continuation line missing indentation or outdented
./litex/gen/genlib/fifo.py:196:17: W503 line break before binary operator
./litex/gen/genlib/fsm.py:42:21: E127 continuation line over-indented for visual indent
./litex/gen/genlib/fsm.py:42:21: W503 line break before binary operator
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./litex/gen/genlib/fsm.py:43:21: W503 line break before binary operator
./litex/gen/genlib/fsm.py:46:21: E127 continuation line over-indented for visual indent
./litex/gen/genlib/fsm.py:46:21: W503 line break before binary operator
./litex/gen/genlib/fsm.py:75:80: E501 line too long (83 > 79 characters)
./litex/gen/genlib/fsm.py:77:80: E501 line too long (82 > 79 characters)
./litex/gen/genlib/fsm.py:78:80: E501 line too long (92 > 79 characters)
./litex/gen/genlib/fsm.py:159:80: E501 line too long (91 > 79 characters)
./litex/gen/genlib/fsm.py:162:80: E501 line too long (80 > 79 characters)
./litex/gen/genlib/fsm.py:171:80: E501 line too long (91 > 79 characters)
./litex/gen/genlib/fsm.py:176:80: E501 line too long (91 > 79 characters)
./litex/gen/genlib/io.py:20:80: E501 line too long (110 > 79 characters)
./litex/gen/genlib/io.py:37:80: E501 line too long (111 > 79 characters)
./litex/gen/genlib/io.py:76:80: E501 line too long (101 > 79 characters)
./litex/gen/genlib/io.py:95:80: E501 line too long (102 > 79 characters)
./litex/gen/genlib/io.py:96:1: W391 blank line at end of file
./litex/gen/genlib/misc.py:53:9: E128 continuation line under-indented for visual indent
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./litex/gen/genlib/misc.py:56:5: E124 closing bracket does not match visual indentation
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./litex/gen/genlib/misc.py:88:13: E124 closing bracket does not match visual indentation
./litex/gen/genlib/record.py:113:11: E128 continuation line under-indented for visual indent
./litex/gen/genlib/record.py:158:80: E501 line too long (83 > 79 characters)
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./litex/gen/genlib/record.py:165:80: E501 line too long (84 > 79 characters)
./litex/gen/genlib/record.py:192:80: E501 line too long (94 > 79 characters)
./litex/gen/genlib/resetsync.py:18:80: E501 line too long (110 > 79 characters)
./litex/gen/genlib/roundrobin.py:27:25: E124 closing bracket does not match visual indentation
./litex/gen/genlib/sort.py:48:17: E124 closing bracket does not match visual indentation
./litex/soc/tools/litex_term.py:41:13: E221 multiple spaces before operator
./litex/soc/tools/litex_term.py:42:13: E221 multiple spaces before operator
./litex/soc/tools/litex_term.py:45:16: E221 multiple spaces before operator
./litex/soc/tools/litex_term.py:47:16: E221 multiple spaces before operator
./litex/soc/tools/litex_term.py:48:14: E221 multiple spaces before operator
./litex/soc/tools/litex_term.py:144:80: E501 line too long (95 > 79 characters)
./litex/soc/tools/litex_term.py:173:80: E501 line too long (84 > 79 characters)
./litex/soc/tools/litex_term.py:180:63: W291 trailing whitespace
./litex/soc/tools/litex_term.py:207:30: E703 statement ends with a semicolon
./litex/soc/tools/litex_term.py:216:17: E101 indentation contains mixed spaces and tabs
./litex/soc/tools/litex_term.py:216:17: W191 indentation contains tabs
./litex/soc/tools/litex_term.py:285:80: E501 line too long (108 > 79 characters)
./litex/soc/tools/mkmscimg.py:27:80: E501 line too long (103 > 79 characters)
./litex/soc/tools/mkmscimg.py:29:80: E501 line too long (110 > 79 characters)
./litex/soc/tools/mkmscimg.py:30:80: E501 line too long (116 > 79 characters)
./litex/soc/tools/remote/comm_pcie.py:42:80: E501 line too long (87 > 79 characters)
./litex/soc/tools/remote/comm_uart.py:10:5: E301 expected 1 blank line, found 0
./litex/soc/tools/remote/comm_udp.py:31:80: E501 line too long (82 > 79 characters)
./litex/soc/tools/remote/csr_builder.py:44:80: E501 line too long (97 > 79 characters)
./litex/soc/tools/remote/csr_builder.py:79:80: E501 line too long (101 > 79 characters)
./litex/soc/tools/remote/etherbone.py:207:5: E303 too many blank lines (2)
./litex/soc/tools/remote/etherbone.py:264:45: E127 continuation line over-indented for visual indent
./litex/soc/tools/remote/etherbone.py:334:80: E501 line too long (94 > 79 characters)
./litex/soc/tools/remote/etherbone.py:359:80: E501 line too long (87 > 79 characters)
./litex/soc/tools/remote/litex_client.py:10:80: E501 line too long (103 > 79 characters)
./litex/soc/tools/remote/litex_client.py:33:80: E501 line too long (84 > 79 characters)
./litex/soc/tools/remote/litex_client.py:54:80: E501 line too long (81 > 79 characters)
./litex/soc/tools/remote/litex_server.py:6:80: E501 line too long (94 > 79 characters)
./litex/soc/tools/remote/litex_server.py:41:21: E101 indentation contains mixed spaces and tabs
./litex/soc/tools/remote/litex_server.py:41:21: W191 indentation contains tabs
./litex/soc/tools/remote/litex_server.py:48:38: E711 comparison to None should be 'if cond is not None:'
./litex/soc/tools/remote/litex_server.py:49:80: E501 line too long (91 > 79 characters)
./litex/soc/tools/remote/litex_server.py:52:37: E711 comparison to None should be 'if cond is not None:'
./litex/soc/tools/remote/litex_server.py:83:1: E302 expected 2 blank lines, found 1
./litex/soc/tools/remote/litex_server.py:92:80: E501 line too long (89 > 79 characters)
./litex/soc/tools/remote/litex_server.py:93:80: E501 line too long (81 > 79 characters)
./litex/soc/tools/remote/litex_server.py:104:19: E701 multiple statements on one line (colon)
./litex/soc/cores/identifier.py:9:80: E501 line too long (80 > 79 characters)
./litex/soc/cores/timer.py:27:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/timer.py:30:13: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:35:80: E501 line too long (80 > 79 characters)
./litex/soc/cores/flash/nor_flash_16.py:38:21: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:41:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:44:13: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:58:80: E501 line too long (91 > 79 characters)
./litex/soc/cores/flash/nor_flash_16.py:60:17: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:61:13: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:69:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:72:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:75:13: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:78:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:79:13: E128 continuation line under-indented for visual indent
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./litex/soc/cores/flash/nor_flash_16.py:83:13: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:86:13: E128 continuation line under-indented for visual indent
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./litex/soc/cores/flash/nor_flash_16.py:91:13: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/nor_flash_16.py:94:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:95:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:96:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:97:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:98:13: E128 continuation line under-indented for visual indent
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./litex/soc/cores/flash/nor_flash_16.py:102:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:103:13: E128 continuation line under-indented for visual indent
./litex/soc/cores/flash/nor_flash_16.py:104:9: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/spi_flash.py:23:20: E227 missing whitespace around bitwise or shift operator
./litex/soc/cores/flash/spi_flash.py:23:24: E228 missing whitespace around modulo operator
./litex/soc/cores/flash/spi_flash.py:24:21: E227 missing whitespace around bitwise or shift operator
./litex/soc/cores/flash/spi_flash.py:35:80: E501 line too long (86 > 79 characters)
./litex/soc/cores/flash/spi_flash.py:52:9: E303 too many blank lines (2)
./litex/soc/cores/flash/spi_flash.py:84:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/spi_flash.py:89:17: E124 closing bracket does not match visual indentation
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./litex/soc/cores/flash/spi_flash.py:102:80: E501 line too long (104 > 79 characters)
./litex/soc/cores/flash/spi_flash.py:110:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/spi_flash.py:115:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/flash/spi_flash.py:132:18: E261 at least two spaces before inline comment
./litex/soc/cores/uart/core.py:34:17: E124 closing bracket does not match visual indentation
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./litex/soc/cores/uart/core.py:51:17: E124 closing bracket does not match visual indentation
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./litex/soc/cores/uart/core.py:56:80: E501 line too long (99 > 79 characters)
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./litex/soc/cores/uart/core.py:89:21: E128 continuation line under-indented for visual indent
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./litex/soc/cores/uart/core.py:91:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/uart/core.py:99:80: E501 line too long (99 > 79 characters)
./litex/soc/cores/uart/core.py:100:17: E124 closing bracket does not match visual indentation
./litex/soc/cores/uart/core.py:108:80: E501 line too long (80 > 79 characters)
./litex/soc/cores/cpu/picorv32/core.py:59:61: E261 at least two spaces before inline comment
./litex/soc/cores/cpu/picorv32/core.py:72:51: E261 at least two spaces before inline comment
./litex/soc/cores/cpu/picorv32/core.py:87:14: E124 closing bracket does not match visual indentation
./litex/soc/cores/cpu/picorv32/core.py:100:14: E124 closing bracket does not match visual indentation
./litex/soc/cores/cpu/lm32/core.py:19:36: E127 continuation line over-indented for visual indent
./litex/soc/cores/cpu/lm32/core.py:19:80: E501 line too long (106 > 79 characters)
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./litex/soc/cores/cpu/lm32/core.py:62:80: E501 line too long (93 > 79 characters)
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./litex/soc/cores/cpu/lm32/core.py:64:80: E501 line too long (83 > 79 characters)
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./litex/soc/cores/spi/core.py:40:13: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:107:25: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:109:25: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:119:25: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:132:21: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:134:21: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:143:21: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:145:21: E124 closing bracket does not match visual indentation
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./litex/soc/cores/spi/core.py:147:21: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/csr.py:11:80: E501 line too long (83 > 79 characters)
./litex/soc/interconnect/csr.py:52:80: E501 line too long (111 > 79 characters)
./litex/soc/interconnect/csr.py:56:80: E501 line too long (93 > 79 characters)
./litex/soc/interconnect/csr.py:63:80: E501 line too long (93 > 79 characters)
./litex/soc/interconnect/csr.py:68:80: E501 line too long (82 > 79 characters)
./litex/soc/interconnect/csr.py:79:80: E501 line too long (80 > 79 characters)
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./litex/soc/interconnect/csr.py:86:80: E501 line too long (85 > 79 characters)
./litex/soc/interconnect/csr.py:88:80: E501 line too long (86 > 79 characters)
./litex/soc/interconnect/csr.py:138:80: E501 line too long (87 > 79 characters)
./litex/soc/interconnect/csr_bus.py:21:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/csr_bus.py:30:80: E501 line too long (82 > 79 characters)
./litex/soc/interconnect/csr_bus.py:43:80: E501 line too long (80 > 79 characters)
./litex/soc/interconnect/csr_bus.py:69:80: E501 line too long (101 > 79 characters)
./litex/soc/interconnect/csr_bus.py:70:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/csr_bus.py:76:80: E501 line too long (113 > 79 characters)
./litex/soc/interconnect/csr_bus.py:80:80: E501 line too long (100 > 79 characters)
./litex/soc/interconnect/csr_bus.py:92:80: E501 line too long (85 > 79 characters)
./litex/soc/interconnect/csr_bus.py:95:80: E501 line too long (102 > 79 characters)
./litex/soc/interconnect/csr_bus.py:120:31: E502 the backslash is redundant between brackets
./litex/soc/interconnect/csr_bus.py:121:21: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/csr_bus.py:121:35: E502 the backslash is redundant between brackets
./litex/soc/interconnect/csr_bus.py:122:21: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/csr_bus.py:125:80: E501 line too long (91 > 79 characters)
./litex/soc/interconnect/csr_eventmanager.py:14:80: E501 line too long (89 > 79 characters)
./litex/soc/interconnect/csr_eventmanager.py:16:80: E501 line too long (107 > 79 characters)
./litex/soc/interconnect/csr_eventmanager.py:58:80: E501 line too long (83 > 79 characters)
./litex/soc/interconnect/csr_eventmanager.py:86:80: E501 line too long (80 > 79 characters)
./litex/soc/interconnect/stream.py:7:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/stream.py:23:80: E501 line too long (80 > 79 characters)
./litex/soc/interconnect/stream.py:27:80: E501 line too long (89 > 79 characters)
./litex/soc/interconnect/stream.py:146:80: E501 line too long (81 > 79 characters)
./litex/soc/interconnect/stream.py:169:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:172:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:175:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:176:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream.py:177:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:213:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:216:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:264:5: E125 continuation line with same indent as next logical line
./litex/soc/interconnect/stream.py:264:9: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream.py:279:29: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream.py:314:9: E303 too many blank lines (2)
./litex/soc/interconnect/stream.py:325:80: E501 line too long (84 > 79 characters)
./litex/soc/interconnect/stream.py:344:1: E402 module level import not at top of file
./litex/soc/interconnect/stream.py:345:1: E402 module level import not at top of file
./litex/soc/interconnect/stream.py:347:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/stream.py:353:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/stream.py:356:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/stream.py:365:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/stream.py:377:80: E501 line too long (101 > 79 characters)
./litex/soc/interconnect/stream.py:413:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:427:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:431:80: E501 line too long (85 > 79 characters)
./litex/soc/interconnect/stream.py:453:80: E501 line too long (89 > 79 characters)
./litex/soc/interconnect/stream.py:469:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:472:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:477:80: E501 line too long (107 > 79 characters)
./litex/soc/interconnect/stream.py:492:80: E501 line too long (85 > 79 characters)
./litex/soc/interconnect/stream.py:504:80: E501 line too long (107 > 79 characters)
./litex/soc/interconnect/stream.py:525:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:528:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:531:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream.py:532:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream.py:533:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:11:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/stream_packet.py:29:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:36:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/stream_packet.py:38:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/stream_packet.py:176:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:177:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:178:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:185:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:191:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:192:21: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:193:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:205:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:206:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/stream_packet.py:215:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:216:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:220:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:221:17: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/stream_packet.py:228:21: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/stream_packet.py:232:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:233:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:234:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:235:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:236:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:240:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:241:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:264:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:265:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:266:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:272:17: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/stream_packet.py:288:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:289:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:290:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:293:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:297:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:298:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:303:21: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:304:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:310:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_packet.py:320:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/stream_packet.py:321:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/stream_packet.py:324:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_sim.py:11:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/stream_sim.py:118:80: E501 line too long (88 > 79 characters)
./litex/soc/interconnect/stream_sim.py:174:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/stream_sim.py:189:6: W292 no newline at end of file
./litex/soc/interconnect/wishbone.py:13:1: E302 expected 2 blank lines, found 1
./litex/soc/interconnect/wishbone.py:40:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/wishbone.py:113:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:123:80: E501 line too long (82 > 79 characters)
./litex/soc/interconnect/wishbone.py:127:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:136:80: E501 line too long (103 > 79 characters)
./litex/soc/interconnect/wishbone.py:167:80: E501 line too long (92 > 79 characters)
./litex/soc/interconnect/wishbone.py:171:80: E501 line too long (82 > 79 characters)
./litex/soc/interconnect/wishbone.py:172:80: E501 line too long (84 > 79 characters)
./litex/soc/interconnect/wishbone.py:191:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbone.py:200:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/wishbone.py:204:17: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbone.py:210:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/wishbone.py:220:21: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbone.py:223:17: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/wishbone.py:227:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/wishbone.py:229:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:236:21: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:237:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:238:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:239:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:240:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:246:32: E261 at least two spaces before inline comment
./litex/soc/interconnect/wishbone.py:247:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:263:9: E303 too many blank lines (2)
./litex/soc/interconnect/wishbone.py:268:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:274:80: E501 line too long (80 > 79 characters)
./litex/soc/interconnect/wishbone.py:279:80: E501 line too long (82 > 79 characters)
./litex/soc/interconnect/wishbone.py:310:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:311:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:312:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:325:80: E501 line too long (113 > 79 characters)
./litex/soc/interconnect/wishbone.py:328:9: E303 too many blank lines (2)
./litex/soc/interconnect/wishbone.py:338:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:339:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:343:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:346:21: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:350:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:353:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:359:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:360:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:361:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:362:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:365:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:366:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:367:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:368:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:369:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:370:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:371:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:373:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:376:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:377:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:378:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:379:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:382:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:385:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:386:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:388:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:394:29: E261 at least two spaces before inline comment
./litex/soc/interconnect/wishbone.py:394:80: E501 line too long (85 > 79 characters)
./litex/soc/interconnect/wishbone.py:411:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:418:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:428:80: E501 line too long (81 > 79 characters)
./litex/soc/interconnect/wishbone.py:462:80: E501 line too long (86 > 79 characters)
./litex/soc/interconnect/wishbone.py:473:80: E501 line too long (94 > 79 characters)
./litex/soc/interconnect/wishbone.py:475:80: E501 line too long (93 > 79 characters)
./litex/soc/interconnect/wishbone.py:484:80: E501 line too long (88 > 79 characters)
./litex/soc/interconnect/wishbone.py:504:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:505:80: E501 line too long (84 > 79 characters)
./litex/soc/interconnect/wishbone.py:507:80: E501 line too long (96 > 79 characters)
./litex/soc/interconnect/wishbone.py:508:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:516:9: E303 too many blank lines (2)
./litex/soc/interconnect/wishbone.py:545:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:546:21: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:547:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:558:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:560:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:563:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:564:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:569:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:571:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbone.py:581:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:582:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:583:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:584:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:586:18: E127 continuation line over-indented for visual indent
./litex/soc/interconnect/wishbone.py:588:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:589:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:592:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:593:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:594:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/wishbone.py:596:9: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:598:13: E128 continuation line under-indented for visual indent
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./litex/soc/interconnect/wishbone.py:606:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:609:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbone.py:623:80: E501 line too long (90 > 79 characters)
./litex/soc/interconnect/wishbone.py:637:80: E501 line too long (100 > 79 characters)
./litex/soc/interconnect/wishbone.py:638:17: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:649:80: E501 line too long (82 > 79 characters)
./litex/soc/interconnect/wishbone.py:666:80: E501 line too long (85 > 79 characters)
./litex/soc/interconnect/wishbone.py:666:85: E502 the backslash is redundant between brackets
./litex/soc/interconnect/wishbone.py:667:21: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbone.py:670:80: E501 line too long (91 > 79 characters)
./litex/soc/interconnect/wishbonebridge.py:28:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbonebridge.py:30:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbonebridge.py:40:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbonebridge.py:61:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbonebridge.py:63:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbonebridge.py:74:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbonebridge.py:79:17: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbonebridge.py:82:13: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbonebridge.py:85:13: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbonebridge.py:88:13: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbonebridge.py:97:21: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbonebridge.py:98:25: E128 continuation line under-indented for visual indent
./litex/soc/interconnect/wishbonebridge.py:99:21: E124 closing bracket does not match visual indentation
./litex/soc/interconnect/wishbonebridge.py:101:17: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbonebridge.py:111:17: E124 closing bracket does not match visual indentation
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./litex/soc/interconnect/wishbonebridge.py:121:13: E128 continuation line under-indented for visual indent
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boot_helper with or1k

or1k_linux branch was using: boot_helper(r1, r2, r3, addr + 0x100);
Understand if it was needed and why: https://groups.google.com/d/msg/linux-litex/hGsnCRemp7Q/phWpdrvtAwAJ

SH2/J-core support

The free SH2 core- aka J-core- is written in VHDL. In principle, J-core/SH2 should work already with Xilinx cores- someone just needs to port the Wishbone interface, startup code, etc :).

For ice40 toolchains, there is essentially no VHDL toolchain that targets yosys. I was fortunate enough to talk to J-core's creator on IRC, and he had this to say:

• yosys support is something they've wanted for a while, but J-core uses many features of VHDL that don't translate to Verilog as-is.
• The nvc VHDL simulator is already capable of simulating J-core.
• Synthesizing VHDL is more complicated than Verilog, to the extent that you essentially need a simulator to instantiate parts of a VHDL design (this is known as VHDL elaboration).
• The best way forward is to extend nvc to output Verilog at a lower-level than users would normally write. nvc's LLVM backend can handle VHDL elaboration that needs to occur before emitting Verilog.

Link to the full conversation: http://ix.io/1ngU

Land minimal / ice40 optimized version of vexriscv

Currently VexRISCV only has a full and debug variants set up. It would be good to have lite and minimal versions added too.

I believe @cr1901 was looking into this.

Allow Yosys to be used for synthesis with Vivado

Reopening #114 as an issue:

The aim here is to allow Yosys to be used for the synthesis step while Vivado remains being used for place and route. (Eventually I hope to also replace Vivado with something based on nextpnr or vpr.)

• Add a (* keep *) attribute to IDELAYCTRL. no longer needed.
• Check no VHDL files are in the source output.
• Add the yosys step to the build_top.sh script.
• Actually test the output bitstream.
• Compare Vivado and Yosys results for synthesis.

Fix TPTP boot with RISC-V

Working:
./sim.py --with-ethernet --cpu-type=lm32

Not working:
./sim.py --with-ethernet --cpu-type=vexriscv
./sim.py --with-ethernet --cpu-type=picorv32

Probably related to endianness.

Need investigating by passing endianness to Ethernet MAC:
https://github.com/enjoy-digital/liteeth/blob/master/liteeth/core/mac/__init__.py#L10

And enabling microudp debug info:
https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/libnet/microudp.c#L12

Standardize variant names across different CPU types?

VexRISCV uses
variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")

picorv32 uses;
variant == "minimal":

mor1kx uses
assert variant in (None, "linux"), "Unsupported variant %s" % variant

lm32 uses:
assert variant in (None, "lite", "minimal"), "Unsupported variant %s" % variant

I had some older thoughts at https://github.com/timvideos/litex-buildenv/wiki/CPU-Variants

I think we need;

• minimal
• standard
• linux
• debug versions (?)

Add TinyFPGA EX support

• Verify ECP5 diamond build support.
• Verify programmer support.
• Create or reuse HyperRAM core.
• Port LiteSDCard to ECP5. (adapt primitives).

RISC-V: use riscv32 toolchain if riscv64 toolchain is not found

simulation shouldn't run as root user

litex/litex/build/sim/verilator.py

Line 129 in db6c88b

sudo obj_dir/Vdut

The simulation still works with the sudo being removed. I'd avoid having code running as root when it's not necessary.

crt0 doesn't copy data section into RAM?

There seems to be some confusion around if the data section should be copied to RAM.

If the program is executing from a read only location (ROM, spiflash, etc) - then the crt0 needs to copy the data section into RAM.
If the program is executing from a read/write location (SRAM, DDR, etc) - then the crt0 doesn't need to do anything (as the data section can be modified in place).

Both picorv32 and lm32 have a EXECUTE_IN_PLACE define which does the data section copy.

However, vexriscv and or1k and minerva are missing this.

Naming this EXECUTE_IN_PLACE is kind of misleading, as the reason the copy needs to occur is because the place it is executing from is read only.