erickmari/hdl-bitnet-1.58

Transformer Bitnet en Verilog

Hi, my name is Erick Marín Rojas and:

• 🐎 From Guanacaste, Costa Rica 🇨🇷
• 🔭 I’m currently working on graduating from the UCR with a bachelor in EE.
• 🌱 I’m currently figuring out what my projects will be.
• 👯 I’m looking to collaborate on anything that gets me to learn the ropes in digital design (for ML inference).
• 🤔 I’m looking for help with the previous point.
• 💬 Ask me about corn.
• 📫 How to reach me: [email protected]
• 😄 Pronouns: N/A
• ⚡ Fun fact: There's a lot of selenium in cas.

hdl-bitnet-1.58's Issues

Book

Hi Erick I have a small gift for you. If you like to learn about the system verilog, VHDL & Risc-V assembly then there are a links which can help you.
Link 1 Sarah Harris & David Harris Digital Design and Computer Architecture
Link 2 Learning Journey how to write system verilog testbench in C++ using Verilator tool
Book:-
https://github.com/muhammadtalhasami/sv_verilator/tree/main/Book

Verilator:-
https://github.com/muhammadtalhasami/sv_verilator

I hope you will like this small gift 🎁😊