ettusresearch/rfnoc-pfb-channelizer

RFNoC out-of-tree module for a channelizer

rfnoc-pfb-channelizer's Issues

Update for Vivado 2017.4 & uhd-fpga master branch?

Hi guys,

Looking to test out this channelizer...

Is there any plan to update IP to Vivado 2017.4 and target the uhd-fpga master branch? I think the only major difference ought to be the axi_wrapper, but I'm not 100% sure.

EJ

Point to up-to-date version in Theseus Cores

It should be noted that the most up-to-date version of this core has moved to the Theseus Cores project:
https://gitlab.com/theseus-cores/theseus-cores/tree/master/fpga-rfnoc/m2_channelizer

This repository isn't building for me with UHD 3.15, whereas the Theseus Cores version is working as expected. I recommend pointing to this repository in the README.

"collision detected": multiple drivers in pfb_2x.v

Hi all,

I'm just trying to simulate the noc_block_channelizer_tb from the master branch, and I'm running into a similar problem as the comment here: #4 (comment)

To be specific, I'm using the master branch of rfnoc-pfb-channelizer and uhd-fpga is set to Oct 2017 (git SHA: 434943bf). I'm on Vivado 2015.4, since I assume that was the last compatible version of Vivado that worked with the pfb-channelizer.

The simulation does not complete, and I get consistent warnings from the console when running. A few examples:

Warning: blk_mem_gen_v8_3_1 WARNING: collision detected: A write address: UUUUUUUUU, B read address: 000000000

Time: 10 ns  Iteration: 1  Process: /noc_block_channelizer_tb/noc_block_channelizer/channelizer_top/circ_buffer/circ_buff_0/U0/native_mem_module/mem_module/async_coll/line__4265  File: /home/ejk/fpga-build/polychan-2015.4/src/rfnoc-pfb-channelizer/rfnoc/testbenches/noc_block_channelizer_tb/xsim_proj/xsim_proj.ip_user_files/ipstatic/blk_mem_gen_v8_3_1/simulation/blk_mem_gen_v8_3.vhd
Warning: blk_mem_gen_v8_3_1 WARNING: collision detected: A write address: UUUUUUUUU, B read address: 000000000

Time: 10 ns  Iteration: 1  Process: /noc_block_channelizer_tb/noc_block_channelizer/channelizer_top/circ_buffer/circ_buff_1/U0/native_mem_module/mem_module/async_coll/line__4265  File: /home/ejk/fpga-build/polychan-2015.4/src/rfnoc-pfb-channelizer/rfnoc/testbenches/noc_block_channelizer_tb/xsim_proj/xsim_proj.ip_user_files/ipstatic/blk_mem_gen_v8_3_1/simulation/blk_mem_gen_v8_3.vhd
Note: Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior.
Time: 20 ns  Iteration: 1  Process: /noc_block_channelizer_tb/noc_block_channelizer/channelizer_top/circ_buffer/circ_buff_0/U0/native_mem_module/mem_module/line__3418  File: /home/ejk/fpga-build/polychan-2015.4/src/rfnoc-pfb-channelizer/rfnoc/testbenches/noc_block_channelizer_tb/xsim_proj/xsim_proj.ip_user_files/ipstatic/blk_mem_gen_v8_3_1/simulation/blk_mem_gen_v8_3.vhd
Warning: blk_mem_gen_v8_3_1 WARNING: collision detected: A write address: UUUUUUUUU, B read address: 000000000

It appears this commit may introduce a few of the problems in pfb_2x.v: 0491635

For example, the code here changes register names from phase_d1/phase_d2/phase_d3 to phase_d[1/2/3] which conflicts with the existing phase_d variable in the source code.

I'm not sure if this is the only problem, but it sure seems suspicious.

Thoughts?
EJ