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View Code? Open in Web Editor NEWVerilog models for the GAL22V10 and select PAL devices.
Verilog models for the GAL22V10 and select PAL devices.
Hello,
This is the input file:
http://members.aon.at/~aklamme4/scratch/dff2.jed
This is the file I get from j2v:
http://members.aon.at/~aklamme4/scratch/dff2.v
This I the testbed:
http://members.aon.at/~aklamme4/scratch/DFF_bench.v
It tests some FFs with different inversions, AR and (emulated)clock enable.
When I try to simulate it, the 22 SOP inputs seem (bit)reversed...
I believe it happens around line 155 in galpal_22V10.v (wire [21:0] prod_in)
If I try to un-reverse them in the rtl file, the simulation seems to hang...
It might be icarus verilog( I am using the latest version from their GIT repository).. It might also be the .jed file...
Any ideas?
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