The glasgow from glasgowembedded

Use an FX2LP in a BGA package?

We can save a dollar if we go for 56-ball 0.5 mm pitch VFBGA package. We only need to route out two rows of balls at most, so it seems fine that it's 0.5 mm pitch. Should we?

Make SYNC pullup smaller

The FPGA has ridiculously powerful drivers (what, 10 mA?) so if we use a pullup smaller than 1k we can go well into MHz range. Useful, because the PLL has a minimum frequency of 16 MHz--can we get that high?

Expose hardware revision and serial number via USB descriptors

This needs libfx2 support for editing descriptors before sending them back.

IC footprints

Cypress CY7C68013A-LXI

Unfortunately, some issues with the footprint: KiCad/kicad-symbols#289 (comment)

Add serial number storage to CYP_MEM

This should be compatible with both C0 and C2 loads--mimic a C2 write to address 0?

TI DAC081C081CIMK TSOT-6

Nothing closely related. Package seems unusual, needs close attention.

Add tests to program-ice40 applet

These should serve as an example of writing applet tests.

Add an USR LED connected to FPGA

Since we now have a lot of I/O in the FPGA we can afford this. It should be white. This means moving D1-D5 upwards and shifting R3/C13 a bit.

ON Semi FXMA108BQX QFN-20

Nothing related, the high aspect ratio QFN-20 almost definitely doesn't exist yet.

Slew rate limiting resistors

Two arrays of four resistors per port. I'm not sure yet what the values should be; worst case, we can always populate with 0R and decide later.

TI ADC081C021CIMM MSOP-8

Nothing closely related, seems to use an existing package.

Measure FXMA108 slew rate

Needed for #35.

Implement USB benchmarks

At least:

"Source": device emits an endless stream of data via one or two FIFOs, host validates (simulates a logic analyzer subtarget)
"Sink": host emits an endless stream of data via one or two FIFOs, device validates (simulates an I2S protocol subtarget)
"Loopback": host emits an endless stream of data via one or two FIFOs, device puts it all back into the other end of the pipe, host validates (simulates an SPI protocol subtarget)

Test/loopback PCB

When (at this point, apparently not "if") we do a production run we'll need to do QA, and for that we should use a simple board that plugs into both ports and connects them to each other. It should also have LEDs (buffered to Vioa, since the level shifters cannot drive a LED directly) for visual verification.

TI LM3880MFX-1AF SOT-23-5

TI TPS73101DBVR SOT-23-5

KiCAD has a closely related TPS763xx series, the TPS731 series probably just needs to be a few aliases.

Allow flashing CYP_MEM with firmware

Implement SPI subtarget

This should demonstrate:

how to do bidirectional communication in a subtarget
how to implement an interactive subtarget

Disable ~OEQ while flashing FPGA or in alert?

It looks like resetting the FPGA intrinsically tristates all pins (verify!), and it's not clear that tristating every port (~OEQ is routed to all buffers) on alert in any port is the right thing to do.

FX2_MEM EEPROM is absurdly slow

We should maybe use a faster one if it's not much more expensive, this is pretty annoying.
This also likely applies to ICE_MEM EEPROM.

J1 does not clear the board outline

Needs to be moved left ~1mm (consult drawing!!)

R16 has wrong Mouser_PN

It's for 560R, should be 600R.

Cache bitstreams

Synthesis and PAR are slow, rerunning them on every invocation is wasteful, and explicit --no-build is awful.

Needs extra care so that it works on:

Linux
macOS
Windows

Incorrect Mouser PN for R19, R22

49.9 Ohm, need 49.9 kOhm.

ON Semi CAT24M01WI-GT3

There aren't any 24M01 variants in KiCAD, but this only needs a new symbol.

Make status registers possible

Right now all registers are storage registers (i.e. writable by host only), which makes the whole thing kind of useless.

Develop a tool to validate capacitor/resistor values against Mouser API

Add IFCLK test point

I'm observing some strange issues related to post-bitstream-upload reset and CDONE is currently not easily accessible at all.

Allow flashing bitstream to ICE_MEM

Lattice ICE40UP5K-SG48ITR QFN-48

Needs a new FPGA_Lattice category.

Use a dedicated USB protection IC instead of a regular fast-blow fuse

If you short Vio to GND for like a millisecond it blows instantly. Source: shorted Vio to GND for like a millisecond.

ENVA/ENVB should have pulldowns, not pullups

Describe Device, Target, Applet APIs

GlasgowDevice
GlasgowTarget
GlasgowApplet

Migrate to iCE40HX8K-BG121

BG121 is a new 0.8 mm pitch package. Mouser only has it via drop shipment MOQ 260, Digikey has MOQ 1. Investigate if CT256 is a better option after all.

Crystal pinout is inverted

We have xtal on pins 2-4, the package has it on pins 1-3.

Make FX2 bus arbiter prevent starvation

Use a leaky bucket algorithm to limit per-FIFO bursts to 16 bytes (or a configurable value).

Implement MPSSE subtarget and FTDI emulation mode

This is kind of annoying because it needs reenumeration logic in the firmware.

Connect ~ENVA, ~ENVB, ~OEQ, ~ALERT to spare FPGA balls

These are all active-low with pullups, so they can be shared by the FPGA and FX2 for added flexibility.

ON Semi CAT24C256WI-GT3 SOIC-8

Alias of Memory_EEPROM/24LC256

Figure out exactly what happens during Vio short-circuit to GND

On revA the fuse blows immediately. Need to check if the current limiting works as designed (probably not since the fuse blows. lol.) and decide what to do about it.

Y1 footprint is way too big

Not actually an issue for the component selected, since it still solders nicely, but this is not what I was expecting at all.

Reduce green LED intensity by two times or so

Lattice iCE40HX8K-BG121 121-ball caBGA

Move R12-R16 to top side

It's a pain in the ass to do double-sided assembly, that's what it is. No need to make it worse.

Implement a self-test routine checking for solder bridges

This is essentially #26-lite; a proper loopback PCB would allow to test input/output on every single pin, but you need to have it. On the other hand, all our I/O are adjacent on both FPGA and FXMA, and being able to quickly eliminate any possible shorts is enormously valuable.

This should run the check twice, once with ~OEQ high and once low, to check for shorts on either side of FXMA.

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