design r0.6

[mossmann]

design r0.6

[mossmann]

Work in progress is here: https://github.com/mossmann/luna/tree/hw-r0.6

[yyrfejx884]

Can you add pin headers to target d- and d+ lines?

[martinling]

Can you add pin headers to target d- and d+ lines?

We're not going to be keen to do that, because those lines are used for high-speed differential data, and stubs are a problem for signal integrity. We already have some short stubs in the D+/D- passthrough to connect the target PHY, but they've been minimised as much as possible.

What would you want to do with headers on those pins? In the r0.6 layout there is already a connection for the FPGA to directly sense the target D+/D- signals via some resistors, so if you want to do additional monitoring of those pins, that can be done via the FPGA.

[yyrfejx884]

There are some cases when you need to put some extra circuit on these lines temporarily for example: https://www.huaweinewos.com/huawei-harmonyos-support-harmony-tp-cable.html
In this case you need to put two pull-ups on the data lines till the fastboot loads then you can remove them and use the usb as normal.

[mossmann]

There are some cases when you need to put some extra circuit on these lines temporarily for example: https://www.huaweinewos.com/huawei-harmonyos-support-harmony-tp-cable.html In this case you need to put two pull-ups on the data lines till the fastboot loads then you can remove them and use the usb as normal.

We won't be adding a D+/D- pin header in r0.6 for the signal integrity reason @martinling mentioned and also due to lack of board area and time (we have already had r0.6 prototype PCBs made). Harmony TP interfacing will have to be done with an external cable or by soldering resistors to the through-hole TARGET A pins.

If you implement the USB communication with Cynthion (not a passthrough host), you could use the additional TARGET port as a place to plug in a small resistor circuit instead of using a special cable.

[mossmann]

Design validation by hardware bring-up progress:

• scope +3V3
• scope +2V5
• scope +1V1
• scope 60 MHz clock
• check idle current
• SWD via J10
• SWD via J6
• RESET button
• PROGRAM button
• CONTROL USB switch
• Apollo USB data
• program FPGA via Apollo
• debug LEDs
• FPGA LEDs
• interactive-test.py
• bulk_in_speed_test.py on TARGET C
• bulk_in_speed_test.py on AUX
• CONTROL/AUX power input diode OR
• CONTROL overvoltage shutoff
• AUX overvoltage shutoff
• TARGET C VBUS passthrough on/off
• CONTROL VBUS passthrough on/off
• AUX VBUS passthrough on/off
• TARGET C VBUS passthrough on by default while powered off
• TARGET C VBUS passthrough on by default while powered on
• CONTROL VBUS passthrough off by default
• AUX VBUS passthrough off by default
• VBUS passthrough up to 21 V
• VBUS passthrough up to 3 A
• write to SPI flash
• configure FPGA from flash
• high speed USB data passthrough
• bulk_in_speed_test.py on CONTROL
• USER button
• J10 power input
• CONTROL CC Rd
• TARGET C Type-C controller I2C
• TARGET C CC I/O
• TARGET C CC Rd while powered off
• TARGET C CC Rd while powered on
• TARGET C CC overvoltage shutoff
• TARGET C SBU overvoltage shutoff
• TARGET C SBU I/O
• AUX Type-C controller I2C
• AUX CC I/O
• AUX CC Rd while powered off
• AUX CC Rd while powered on
• AUX C CC overvoltage shutoff
• AUX C SBU overvoltage shutoff
• AUX SBU I/O
• power monitor I2C
• CONTROL power monitor
• AUX power monitor
• TARGET A power monitor
• TARGET C power monitor
• CONTROL power input shutoff
• AUX power input shutoff
• PMOD A
• PMOD B
• MEZZANINE
• USB analysis
• CONTROL USB reset detection
• TARGET D+/D- monitor
• +3V3 current up to 1 A
• hyperram_diagnostic.py
• FPGA->MCU interrupt
• TARGET A VBUS discharge

[mossmann]

closing as this (and more) has been merged to: https://github.com/greatscottgadgets/cynthion-hardware