View Code? Open in Web Editor
NEW
The project is the final target for Computer composition class of Department of Computer science in Tongji Univerity
Pascal 0.02%
HTML 0.17%
Verilog 0.92%
VHDL 0.55%
SystemVerilog 93.76%
Shell 3.80%
Stata 0.63%
Forth 0.04%
Tcl 0.05%
Batchfile 0.03%
Csound 0.03%
mips-cpu54's Introduction
- This is a cpu implemented in systemVerilog
- The project is the final target for Computer composition class of Department of Computer science in Tongji Univerity
- Vivado 2016.2
- ModelSim PE 10.4c
- My code is totally rubbish, but it will indeed help you pass the online test.
- Change names of REGISTER, and it can change the timming log thoroughly
- update on July 27th in 2018
mips-cpu54's People
Contributors