This repository used to document the progress of the 5-days workshop on Physical design using OpenLANE flow(an orchestra of open source tools put together to build/create an open source community of digital and analog IP's).
- OpenLANE Workshop
- Day Progress & Learnings
- Day 1: Introduction to OpenLANE Flow
- Day 2: Floorplanning and Placement
- Day 3: Standard Cell Analysis
- Day 4: Timing Analysis using OpenSTA and Clock Tree Synthesis
- Day 5: RTS to GDSII Final Steps
- Contact
- Acknowledgment
- References
- For Installation of OpenLANE
During the workshop, most of the labs are performed using a pre-coded picorv32a project.
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Invoking the openLANE using
./flow.tcl -interactive. The chip design is an iterative process, hence interactive mode offers better control and flexibility. -
Load required dependencies of openLANE using following Command.
package require openlane 0.9
All the designs are kept at the /openlane_working_dir/designs. For the workshop, 'picorv32a' design has been used.
The command used for setting up the design with 'LEF' and 'TECH' file. The 'LEF' file format contains information related to the terminals, different layers, dimensions etc, where Tech files contains layer definition and design rule checks(DRC).
Set 'LIB_SYNTH' variable to the ./openlane_dir/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd_tt_025C_1v80.lib. This liberty file contains Standard cell characteristics for 25 Deg Celsius Temperature and 1.8V. Add this variable in the config.tcl file present in the picorv32a folder.
Use command run_synthesis
File resulted from the synthesis
Floorplanning includes placement of I/O pads and macros as well as power planning(Note: OpenLANE flow allows Power Planning post CTS).
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Aspect Ratio: This determine the shape and size of the chip. It is defined as ratio of height to width. Note: Aspect Ratio 1 means shape is square.
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Core Utilization: Core Utilization defined as the total area occupied by the netlist to the total area of the core. if Core Utilization is 0.6 then it means 40% of the area is going to be used for routing purposes.
For more control parameter refer to openLANE configuration Readme
Run Command run_floorplan after adjusting proper control parameters in config.tcl.
Command generates 'DEF' file in the folder /designs/picorv32a/run/<setup-folder>/results/floorplan/
Viewing 'DEF' file using Magic Magic requires three files to view Picorv32a DEF file:
- Magic Tech file: sky130A.tech
- LEF File: Merged.lef
- DEF File: Any Def file generated using this LEF file
Command to run magic:
magic -T <Tech File> lef read <LEF File> def read <DEF File> &
Floorplan result:
After Floorplan, next step(in physical design) is the placement stage. Standard cells has been mapped as per the synthesized netlist and their standard rows are determined by the floorplan.
Placement in OpenLANE happens in two stages. First stage is the Global placement in which placements of the cells are not legalized. Followed by Detailed Placement in which proper legalization is considered.
Run Placement Command: run_placement
Placement Legalization Pass :
Placement result on Magic:
In this section of the workshop, a pre-build inverter was analyzed in the OpenLane flow using ngspice and magic PEX extraction to obtain .spice file of the inverter which further analyzed in the ngspice 31.
To clone the cell use following command: git clone https://github.com/nickson-jose/vsdstdcelldesign
File of interest in the cloned repo is sky130A_inv.mag file and to view the layout of the cell using Magic .tech file is required. Hence, copy the sky130A.tech file to this cloned repo as shown below:
Run command magic -T sky130A.tech sky130A_inv.mag &
To extract the parasitic type following command on the magic terminal:
% extract all
% ext2spice cthresh 0 rthresh 0
% ext2spice
As shown in the above image this command will generate two files 'sky130_inv.ext' and 'sky130_inv.spice'.
In order to do transient simulation in ngspice following changes were made in the file:
- Add pshort.lib and nshort.lib files using '.include' statement.
- As pshort.lib does not have any model by the name of pshort. Hence replace pshort with pshort_model.0. Also, replace nshort with nshort_model.0 for same reason.
- Provide supplies using dc supplies to VA and VSS.
- Provide pulse signal to the port A.
- Add simulation setup: .tran 1n 20n (1ns step and simulation time 20ns)
- Change the scale to 0.01u
- Add .control to perform run inside the same file.
Spice file after all the changes:
Execute Simulation using command: ngspice sky130_inv.spice
Followed by ngspice-> plot y vs time a in the ngspice command line.
Results in following plot:
Input and Output ports should be placed such that port should intersect the odd multiples of tracks pitch especially of the locali and metal layers. This dimension information is presented in the track.info file.
As shown in the above image, li1 layer horizontal track has pitch of 0.46 and offset of 0.23. Here, the offset is half of pitch means tracks are centered around the origin.
Considering that add grid to magic using following command:
% grid 0.46um 0.34um 0.23um 0.17um
Note: type grid help in magic console for more information on grid command
Below image confirms that both A and Y lies on the odd multiples of the track.
Note: Magic could also be used to assign port using the option edit->text.
After confirming that the I/O port of the inverter lies on the tracks, extract the LEF file which contains the abstract information of the cell.
Type lef write in the magic console window. This generates a .lef file in the same directory.
Now to include a custom inverter cell into a openLANE flow, one needs to do cell characterization using either GUNA or any closed source tools. This custom cell characterization will provides liberty files that need to be included in the config.tcl of the project as shown below.(For this workshop these liberty files were provided by the vsd team)
Use same command as shown on the day one with -overwrite tag to remove the past project files. This generates a new merged.lef(present in <design_folder>/run/<run_name>/tmp/merged.lef) with sky130_vsdinv cell defined inside it.
Last two commands were run to include the sky130_vsdinv.lef More information on Nickson Repo
Now, follow the OpenLANE flow like run_synthesis-> run_floorplan -> run_placement and confirm weather custom cell is getting included inside the design flow.
Result:
- After Synthesis: Total 1947 instance of sky130_vsdinv included in the netlist.
- After Placement: Properly aligned sky130_vsdinv cell shown below using magic.
Static Timing Analysis checks for the worst case propagation of all the possible paths for min/max delays. Hence, STA reports WNS(Worst negative slack) and TNS(Total negative slack). To debug the slack violations OpenSTA is used as it is integrated in OpenLANE flow.
File requirement:
- Configuration files (.conf)
- Constraint files (.sdc)
This requires following files:
- Constraint files(.sdc).
- min and max Liberty files
- Verilog file
- SPEF file (Optional)
After setting-up .conf file:
After running OpenSTA on the design with custom cell negative slack was observed(shown below)
This violation can be debugged inside the openSTA by replacing the small buffers with bigger buffers especially for the nets where Fanout is more than 4.
After standard cell placement in OpenLANE, it's time to perform CTS which inserts the clock tree in the design.
Run clock tree synthesis(CTS) in OpenLANE: run_cts
Note: CTS run will generate a new .v file with clock buffers.
Invoke magic using similar command as used in day two but change the DEF file with the file present in CTS folder instead of placement.
As mentioned earlier that in openLANE flow Power distribution network is generated not in the floorplan but after the CTS generation. Hence, it's time to generate PDN network.
Run Command gen_pdn.
Note: Make sure that the .def file env variable should be pointing to *cts.def file instead of placement def.
Like any commercial tool OpenLANE also perform routing in two steps.
- Global routing: This generates routing guides for the netlist while defining layers possible tracks in each guide. This routing is performed by tool named 'Fast Route'
- Detail routing: This performs a exhaustive task in which TritonRoute iteratively route each interconnect using the routing guide generated in Global Route.
Note: In Detail routing time/memory consumption could be controlled by using the 'ROUTING_STRATEGY' variable. If this variable is set to 0 then it would be less optimized with few DRC violations but will be faster and consumes less time and memory whereas if 'ROUTING_STRATEGY' set to 14, it gives very optimized result with clean DRC but takes more time and memory.
To Perform Routing run Command: run_routing
Synthesis File generation while running routing:
Before performing routing, OpenLANE creates two verilog files as shown above: diodes.v and preroute.v
These files contains the diodes used to limit the Antenna generation for the longer nets.
Result after routing:
Once routing has been completed interconnect parasitics can be extracted to perform post-route STA analysis. The parasitics are extracted into a SPEF file. The SPEF extractor is not included within OpenLANE as of now.
Although a python module was provided by the VSD team for SPEF extraction. (TODO: Add the repo link for the SPEF extraction module)
- LEF File
- DEF FIle
Harsh Shukla - Linkedin
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