hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks. It is released as open-source project under the very permissive BSD 3-Clause License.

See documentation on the website: https://hdl-modules.com

The code is designed to be reusable and portable, while having a clean and intuitive interface. Resource utilization is always critical in FPGA projects, so these modules are written to be as efficient as possible. Using generics to enable/disable different features and modes means that resources can be saved when not all features are used. Some entities are very deliberately area optimized, such as the FIFOs, since they are used very frequently in FPGA projects.

More important than anything, however, is the quality. Everything in this project is peer reviewed, has good unit test coverage, and is proven in use in real FPGA designs. All the code is written with readability and maintainability in mind.

The following things can be found, at a glance, in the different modules:

• axi: AXI3/AXI4 Crossbars, FIFOs, CDCs, etc.
• axi_lite: AXI-Lite Crossbars, FIFOs, CDCs, etc.
• bfm: Many BFMs for simulating AXI/AXI-Lite/AXI-Stream.
• common: Miscellaneous, but useful, things that do not fit anywhere else.
• fifo: Synchronous and asynchronous FIFOs with AXI-stream-like handshake interface.
• hard_fifo: Wrappers, with cleaner AXI-stream-like handshake interfaces, around hard FIFO primitives.
• lfsr: Maximum-length linear feedback shift registers for pseudo-random number generation.
• math: Some common math function implementations.
• reg_file: A generic register file and a simulation support package for register operations.
• resync: CDC implementations for different signals and buses, along with proper constraints.
• sine_generator: Professional sinusoid waveform generator (or DDS, NCO).

hdl-modules's Issues

resync_level without input register never uses set_max_delay constraint

Looking at the report_cdc report on a synthesized artyz7 design, there are way more false paths than there should be.

In cases where we instantiate resync_level without an input register but with a clock assigned, we thought the TCL script could use the clock signal to construct a set_max_delay constraint. This does not seem to work, as it falls back to set_false_path. Probably since the clock is unused, it is optimized away.

This means that

• resync_pulse
• resync_slv_level_coherent
• debounce

have an undefined latency. Reconstruct them so they always use a set_max_delay constraint. In the case of debounce, it needs to be re-made completely. Should probably use IOB attribute. Test this in the artyz7 top level somewhere.

Update documentation of resync_level to reflect this.

Enable PIP and APT caching in CI

Was disabled to achieve stability. Can probably be enabled again.

Add test that R and B channels are driven invalid when bus is not valid

Once VUnit/vunit#802 has been merged, expand check in tb_axi_write_bfm.vhd and tb_axi_read_bfm.vhd to check that R and B are 'X' when valid is low.

Consider using VUnit's method for removing strobed out AXI-Stream byte lanes

Seems to be a fix on the way in VUnit:

• VUnit/vunit#798
• VUnit/vunit#799