hehao98/riscv-simulator

A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation

RISC-V Simulator

A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation

It is a simple RISC-V Emulator suppprting user mode RV64I instruction set, from PKU Computer Architecture Labs, Spring 2019. I made my project open source in the hope that others can learn from my code about how to make a CPU Emulator and get a deeper understanding in computer architecture. As it is implemented entirely from scratch (with no code from Prof or TA), I think it's fine to make it open source.

Note that this is just a toy for learning and is NOT a robust and full solution to RISC-V CPU Emulation. Use qemu for that purpose instead.

Features

1. Supporting 54 RISC-V instructions from the RV64I instruction set.
2. Branch perdiction module with a set of branch perdicton algorithms.
3. Simulation of five stage pipeline like that in the "Computer Organization and Design, Hardware/Software Interface" Book.
4. Simulation of cache and various cache eviction strategies.

Compile

mkdir build
cd build
cmake ..
make

Usage

./Simulator riscv-elf-file-name [-v] [-s] [-d] [-b strategy]

Parameters:

1. -v for verbose output, can redirect output to file for further analysis
2. -s for single step execution, often used in combination with -v.
3. -d for creating memory and register history dump in dump.txt
4. -b for branch perdiction strategy (default BTFNT), accepted parameters are AT, NT, BTFNT and BPB.
   • AT: Always Taken
   • NT: Always Not Taken
   • BTFNT: Back Taken Forward Not Taken
   • BPB: Branch Prediction Buffer (2 bit history information)

There are a number of reference RISC-V ELFs and its corresponding assembly code in the riscv-elf/ folder.

Documentation (In Chinese)

See the doc/ folder.

Also, you can see the corresponding blog.

riscv-simulator's Issues

Mistake when handling 2 consecutive branch instruction

Hello, sorry to interupt you after such a long time.

I am a student taking Computer Architecture class CSC3050 in CUHKSZ, one of our assignment involves reproducing the pipeline implementation in this simulator project. After reading codes in your project, my classmate and I find a mistake in decode stage of the pipeline.

The decode stage save branch destination address directly under class Simulator, it may handle 2 consecutive branch instruction wrongly. I've pulled a request with fixed version.

The detail is as follow:

The mistake appears when simulating 2 consecutive branch instruction and the first instruction is predicted wrongly, the simulator will jump to rd record in the 2nd instrution instead of the first instruction.
for example:

bne a0, a1, dest1
bne a0, a2, dest2

when predictor predict not to jump but a0 = a1, the simulator will actually jump to dest2 instead of dest1.

We believe this mistake is caused by the member Simulator->anotherPC and Simulator->predictedPC, they are saved directly under Simulator class, therefore behaved as a global variable during the simulation.

So at the loop when the first branch instruction is to be executed, decode stage deals with the second branch instruction update pair Simulator->anotherPC, Simulator->predictedPC to it's current instrution rd, which contains dest2 and covers dest1, so after that, at execute stage, Simulator->anotherPC no longer saves correct destination dest1 anymore.

The change of fixed version is as follow:

• Shift member Simulator->anotherPC Simulator->predictedPC into DReg struct in simulator.h
• Change all part in simulator.cpp involves these two addresses (e.g. this->anotherPC to this->dRegNew->anotherPC at decode stage), pass this address through stage registers.

We also make a test case that will show different output, it's attached below.
test-doublebranch.zip
The test executable file temp.riscv is compiled by the file temp.c with RV32I instruction set, if simulated correctly, the output will be 1453, but the simulator actually outputs 1644 when choosing NT (always not taken) as predict strategy.

Bugs in Simulator.cpp decode stage when working on SLTU instruction

Hello,
I notice that in decode stage in Simultor.cpp, you might forget to handle with SLTU instruction(RISCV I), which should be in OP_REG case with funct3=3. You still handle SLTU instruction in the remaining stage(execute), so I think you may delete it by mistake.
You can just add SLTU instruction decode handler in decode stage and solve this bug.
Thx.

bug: /src/Cache.cpp:280:12: error: ‘UINT_MAX’ was not declared in this scope

Hi hehao98! I cloned your project on ubuntu16. When I tried to execute
make
a error goes like the title. And I rewrote that line like this :
return uint32_t(-1);
Then I can successfully execute the make command, and I ran your example which is
./Simulator ../riscv-elf/ackermann.riscv
Finally, I got the result just like your's. I don't know how you ran the project because I grep that marco but couldn't find the definition in the Makefile or *.h *.cpp.
Anyway, Thanks your work, it helps me a lot!