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License: Apache License 2.0
Cortex-M MPU library
License: Apache License 2.0
Any plans for Cortex M3 core support? Is the MPU in the M3 much different to the M4?
I have some problems getting it working, but maybe I am just using it wrong.
I have a STM32F411 Nucleo board, so MPU should be supported to my understanding.
I set it up like this:
#[exception]
fn MemoryManagement() -> ! {
rprintln!("Memory management error");
loop {
cortex_m::asm::nop();
}
}
#[entry]
fn main() -> ! {
let mut regions = ArrayVec::new();
let base = cortex_m_rt::heap_start() as usize;
regions.push(Region {
base_addr: base,
size: Size::S32B,
subregions: Subregions::ALL,
executable: false,
permissions: AccessPermission::NoAccess,
attributes: MemoryAttributes::Normal {
shareable: false,
cache_policy: CachePolicy::NonCacheable,
},
});
rprintln!("Configure MPU - base: 0x{:08x}", base);
let mut mpu = unsafe { Mpu::new(core.MPU) };
mpu.configure_unprivileged(®ions);
rprintln!("Try access");
unsafe {
ptr::write_volatile(base as *mut i32, 0);
}
rprintln!("Whoopsie");
loop {
cortex_m::asm::nop();
}
}
My expectation would be, that the point of "Whoopsie" is never reached. And it calls into the fn MemoryManagement
instead.
However, the code just runs past that point.
ArrayVec
tends to optimize relatively badly. I've used it to express the constraint "up to N memory regions", so we'd have to find a different way to express that.
Ideally the generated code shouldn't do more than just store any dynamic values and create a list of Region
s.
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