VSD workshop - Phase Locked Loop(PLL) IC Design!
The following repo is the documentation of learnings and activities done throughout a 2-day workshop on PLL IC Design with SKY130 Technology conducted by VLSI sytem design.
- Introduction to PLL
- Tools Overview and Design Flow
- Circuit Design and Simulation
- Layout Design
- Parasitic Extraction and PLS
- Tapeout
- Acknowledgement
Phase locked loops are important components in any digital circuits. It is responsible for creating a precise clock signal without any noise(frequency or phase).
The above diagram shows basic block diagram of the PLL to be implemented. The functionality of PLL can be decribed as two processes.
- Comparing frequency of reference and ouput(PFD)
- Adjusting frequency to match reference signal(CP and VCO)
The phase frequency detector(PFD) is responsible for comparing the reference signal given as input and the output signal. Then it should produce output which clearly shows the difference of phase. This phase difference is not just in terms of magnitude but it should also show whether the ouput is leading or lagging behind the reference. The ouput of PFD is in digital form.
The CP converts the digital output from PFD to an analog signal. This analog signal is what would control the VCO. The analog ouput from CP is passed through a low pass filter before connecting to the VCO. This low pass filter can help smoothen the signal in addition to stabilizing the feedback loop.
Voltage controlled oscillators are the actual parts which produces alternating digital clock signal. The frequency of this clock signal can be controlled by input voltage, hence the name. VCO can be implemented using simple inverters. A PLL with a frequency divider on its feedback loop is called a clock multiplier PLL. Such a PLL can make clock signals which are multiples of the reference signals.
Design flow of the PLL IC has the following steps:
- Specifications of the IC
- SPICE level circuit development
- Pre-layout simulation
- Layout development
- Parastic Extraction
- Post-layout simulation
- Tapeout
The SKY130 are set of 180nm-130nm technology based process nodes and PDKs(Process Design Kits), provided for free. The content provided in this pdk include:
- io-input-output
- pr-primitives
- sc-standard cell
- hd-high density
- hs-high speed
- lp-low power
- hdll-high density low leakage
The ngspice is an open-source electronic circuit simulator widely used in ciruit design and analog VLSI domain. Ngspice is very simple to get in linux systems. The following terminal command can be used to install it in a linux system.
sudo apt-get install ngspice
Magic is an open-source VLSI layout tool. It is mainly used for making the layout and the parasitic extraction which follows. For SKY130, the latest version of magic needs to be installed and this can be done by directly compiling and "making" the source code. Terminal commands for the same are given below.
sudo apt-get update && sudo apt-get upgrade //update OS
git clone git://opencircuitdesign.com/magic //clone magic repository
sudo apt-get install csh //install csh shell if it is absent
cd magic
./configure //run configure script
make //run make command to compile
sudo make install //install magic
Additionally, many of the files used in this workshop where provided through a github repository.
As mentioned in the design flow, every design starts with determining the specifications. The specifications for PLL to be designed are:
- Corner - 'TT' (Typical-Typical)
- Supply Voltage - 1.8V
- Room Temperature
- VCO mode and PLL mode
- Input Fmin=5Mhz; Fmax=12.5Mhz
- Multiplier - 8x
- Jitter(RMS) < ~20ns
- Duty Cycle - 50%
A simple 2x frequency divider circuit can be obtained by using a single D-flipflop whose output is fed back to its input after passing through an inverter. Cascading 3 such flops can give you 8x divider.
This simple circuit can be drawn as:
Writing this circuit as a spice file:
Pre-layout Simulation
The pre-layout simulation of spice model can be done using the command:
ngspice <spice_file_name>
FD Prelayout Simulation Result
The PFD circuit is designed such that, square(digital) signals with pulse width proportional to phase difference are produced at output. Also two different outputs are used to distinguish between cases when output is leading reference signal and lagging behind reference signal.
Given below are the PFD circuit..
and the spice file.
Pre-layout Simulation
PFD Prelayout Simulation Results
The charge pump circuit with modification considering the leakage current is
and the spice file is
Pre-layout Simulation
CP Prelayout Simulation Result
The VCO circuit is realised with a current starved 3 inverter circuit. Using this method, the delay of inverter can be controlled and thereby the frequency of output clock. frequency of clock = 1/(2 * delay of inverter * no: of inverters)
The circuit is:
and the spice model is
Pre-layout Simulation
VCO Prelayout Simulation Result
The final PLL circuit is the joining of all the other blocks. However in addition to individual simulations, the PLL as a whole also need to be simulated. For this we create the spice file by calling the individual circuits as subcircuits.
Pre-layout Simulation
PLL simulation results
Layout Design is the part in which the circuit is converted to polygons which can be made into GDSII format. Here layout design is done using the Magic tool. The layouts are saved with ".mag" extensions. These files can be opened with command:
magic -T <technology_file_name> <layout_file_name>
Shown below are examples of terminal commands:
The layouts for each circuits are given below:
FD Layout
PFD Layout
CP Layout
VCO Layout
After making each layout, these layouts can be instantiated to make the final PLL layout. This is done using File > Place Instance option.
PLL Layout
Parasitic extraction is the process of extracting the capacitance effects(parasitics) of the circuit realised in the layout. This can be done using the magic tool. The magic tool can do this using extract all command. This can further be converted to a spice file using command ext2spice.
Given below is an example spice file of PFD generated in such a way.
For this example around 43 capacitance have been extracted, the largest capacitance between Vcc and GND.
This spice file is used to perform the post-layout simulation.
The above picture shows post-layout simulation results of PFD spice after parasitic extraction.
The parasitic extraction and post-layout simulation are steps for ensuring fuctionality. The GDS file generation can however be done after creating the layout with magic tool.
GDS file can be created using the option File > Write GDS. Although the GDSII file is considered the final format which is sent for fabrication, the IC designed cannot be send as such. The design need to be "prepared" for fabrication process. This preparation is called the tapeout. Any addition which helps connect the wafer to outside world would come under this preparation. This may include adding I-O ports, UART and other peripherals. Efabless, provides a free "shuttle" which will carry our design . This is the Caravel SoC.
Caravel SoC Structure(as provided in efabless.com)
Within the design for caravel, the IP can be added using Place Instance option within the magic tool. After placing, the inputs and outputs need to be connected to the carvel template.
Adding PLL to caravel
- Kunal Ghosh, Co-founder,VSD
- Lakshmi S, Instructor - 8x PLL Clock Multiplier IP
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