hongxiaoo Goto Github PK

spinalhdl_cnn_accelerator

CNN accelerator implemented with Spinal HDL

spinalhdl_lib

Library in SpinalHDL

spinalhdl_sd_ctrl

spinalhdl 实现 sd 控制器

spinalhdldemo

Demo Sources for Learning Spinal HDL

spinalstuff

ss-bash

Shadowsocks流量管理脚本

ss-panel

Let's talk about cat

ss-panel-v3-mod

Forked from https://github.com/orvice/ss-panel

ssr-backup

ShadowsocksR backups

subversion-edge

subversion edge server docker image

sv-for-design

Systemverilog Design Packages

sync_and_asyn_fifo

同步与异步FIFO

tcp3

Nexys3

tcptransmit

转发TCP网络端口数据至另一个IP端口

temperaturecontrol

A FPGA program controls the temperature by heating the cement resistor or using a fan to blow air.

test

TEST GIT

tool-make-script

Synopsys Design compiler, VCS and Tetra-MAX

tools

tools

tri-mode-ethernet-mac-10-100-1000-

Ethernet-MAC System verilog

triple-speed-ethernet-tester

10/100/1000M Ethernet tester

udp_ip_stack

1G eth UDP / IP Stack

unshc

UnSHc - How to decrypt SHc *.sh.x encrypted file ?

usb3_pipe

USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

usb_system

SpinalHDL USB system for the ULPI based Arrow DECA board

v2rayu

V2rayU,基于v2ray核心的mac版客户端,用于科学上网,使用swift4.2编写,支持vmess,shadowsocks,socks5等服务协议,支持订阅, 支持二维码,剪贴板导入,手动配置,二维码分享等

vdvesta

Welcome to VDVESTA, a shell script auto Custom & Install VESTACP for your CentOS Server Release 7 x86_64. Thanks you for using!

verdvana.github.io

Verdvana‘s Blog

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential.

verilog-arbiter

A look ahead, round-robing parametrized arbiter written in Verilog.

verilog-axi

Verilog AXI components for FPGA implementation