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A fault-injection framework using Chisel and FIRRTL

License: Apache License 2.0

Makefile 2.23% Scala 83.72% M4 0.46% Assembly 5.43% C 8.06% Shell 0.10%
chisel firrtl risc-v rocc rocket-chip fault-injection

chiffre's Introduction

Chained Hierarchical Injection for Fault Resiliency Evaluation (Chiffre)

Build Status

This provides a framework for automatically instrumenting a hardware design with run-time configurable fault injectors. This relies on three major components:

  • A Chisel library that emits annotations marking specific circuit components as fault injectable
  • New FIRRTL passes that instrument the circuit components with run-time configurable fault injectors
  • A utility for configuring fault injectors at run time

More information can be found in a CARRV 2018 workshop paper, Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems:

@inproceedings{eldridge:2018:carrv,
  author = {Eldridge, Schuyler and Buyuktosunoglu, Alper and Bose, Pradip},
  title = {Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems},
  booktitle = {2nd Workshop on Computer Architecture Research with RISC-V (CARRV '18)},
  year = {2018},
}

Examples

There are currently two major usage classes: standalone injection and Rocket Chip-assisted injection.

In Standalone Injection you define and implement a fault injection controller, MyController, that manages a specific scan chain. You then annotate specific circuit components with the isFaulty method indicating which scan chain they belong to and what type of fault injector to use. An overall example of this is shown below.

import chisel3._
import chiffre._

/* A controller for injectors on the "main" scan chain */
class MyController extends Module with ChiffreController {
  val io = IO(new Bundle{})
  lazy val scanId = "main"
  // MyController body with scan chain logic not shown
}

/* A module with faulty components */
class MyModule extends Module with ChiffreInjectee {
  val io = IO(new Bundle{})
  val x = Reg(UInt(1.W))
  val y = Reg(UInt(4.W))
  val z = Reg(UInt(8.W))
  isFaulty(x, "main", classOf[inject.LfsrInjector32])
  isFaulty(y, "main", classOf[inject.StuckAt])
  isFaulty(z, "main", classOf[inject.CycleInjector32])
}

In Rocket-Chip Assisted Injection, the fault controller is a provided Rocket Custom Coprocessor (RoCC) called LeChiffre. This can then be used to orchestrate fault injection experiments in external components or inside Rocket itself. We provide an example patch that makes certain control and status registers (CSRs) in rocket fault injectable and a bare metal test program that makes sure this fault injection is working. You can build an emulator with the correct configuration using the following (note: this will clone the chiffre repository inside of your Rocket Chip clone directory):

git clone https://github.com/freechipsproject/rocket-chip $ROCKETCHIP_DIR
cd $ROCKETCHIP_DIR
git clone https://github.com/ibm/chiffre chiffre
git apply le-chiffre/patches/rocket-chip-fault-cycle.patch
cd emulator
make CONFIG=LeChiffreConfig ROCKETCHIP_ADDONS="chiffre/le-chiffre chiffre"

You can then run the test provided by chiffre/tests (instructions provided in that directory).

chiffre's People

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chiffre's Issues

Trying Chiffre in Rocket Chip

Hello,
I am currently member of a university project in which we utilize the Chipyard framework for simulating CPU designs etc.
The chipyard framework contains RocketChip (the source code of which is located inside the directory of Chipyard and is the same with the source of Rocket on its repository).
The issue, which I don't think has to deal with Chipyard itself, but rather an incompatibility or a misunderstanding from my side is with using Rocket Custom Coprocessor (RoCC).
To be precise, I run the following commands, as mentioned in the readme:

git clone https://github.com/freechipsproject/rocket-chip $ROCKETCHIP_DIR
cd $ROCKETCHIP_DIR
git clone https://github.com/ibm/chiffre chiffre
git apply le-chiffre/patches/rocket-chip-fault-cycle.patch
cd emulator
make CONFIG=LeChiffreConfig ROCKETCHIP_ADDONS="chiffre/le-chiffre chiffre"

Even when trying outside of the chiffre directory, inside an empty directory, after (freshly) cloning both rocket chip and chiffre the patch always fails to apply and I receive the error mentioned on the screenshot bellow:
s
A sidenote: after the git clone command, chiffre is cloned inside a directory called "chiffre", in which i have to enter before running the patch apply command.
Thanks in advance and excuse my ignorance as I am pretty new in processor testing.

Unit Testing

All testing to this point has been handled via modification of rocket-chip, use of LeChiffre to inject faults, and bare metal tests to fiddle with rocket-chip CSRs. This should be migrated to actual unit tests that cover at least the following ares:

  • Firrtl tests
    • FaultInstrumentation Pass
    • ScanChainTransform
    • FaultInstrumentationTransform (a combination of the above two)
  • Chisel tests
    • Trait tests
      • Chiffre Injector
      • Chiffre Injectee
    • Injector tests
      • Cycle
      • Lfsr
      • StuckAt
  • Rocket Chip (Anything here is difficult as it technically requires full access to rocket-chip. This may be worth punting on until rocket-chip is available as a library)
    • LeChiffre
  • More?

Incorrect Bit Widths in Scan Chain with Multiple Faulty Regs

If two Regs are annotated as being faulty with the same type of injector, they are reported in the scan chain to have the same width even if they don't in the Chisel code (it appears to be the minimum of the widths of the registers annotated). For example, if both reg_fflags and reg_frm in CSR.scala are annotated with StuckAt faults, scan-chain.json will report them to have widths of three even though fflags is five bits wide. This doesn't happen when the injectors are different.

I can't tell if this affects the final circuit, but it does affect the scan chain tool's ability to create a bitstream for LeChiffre.

Switch to JSON over YAML

Chsiel/FIRRTL are using JSON for Annotation communication. It likely makes sense to switch to this for scan chain description communication.

Bump for Rocket Chip Master

Get this working with master or rocket-chip. Generally:

  • Switch to rocket-chip's Config over the deprecated cde
  • Use LazyRoCC/diplomacy over RoCC

Handling of Aggregate Types

It might be useful and/or convenient for Chiffre to be able to handle aggregate types itself, without requiring them to be divided into their members, recursively if required, to get ground types. I think this would be useful in addition to handling individual members of aggregate types, so users can specify fault injection on entire registers that have fields or on just some of those fields, depending on what they need.

SRAM Fault Injection

Following on from a discussion with @nandhinic, We need the ability to inject into SRAMs. There are two working examples of how this should work:

  1. A shadow SRAM that stores a bit flip mask. On a read, you read one word from the normal SRAM and one word from the shadow SRAM and xor them together.
  2. (1) augmented with a probability. This adds one configurable register that stores a bit flip probability. On an SRAM read, this determines the probability of a bit flip. Note: this overlays a uniform probability across the entire SRAM.

At this point, pre-bit IID probabilities are possibly desirable, but very expensive. This, like with the existing LFSR injector requires one word storing a probability for each bit flip. If the probabilities are stored as 32-bit integers, then this would mean a 32x increase in area.

[RFC] Injection into Arbitrary Types

Related to #14, #18, an injector should be an injector into arbitrary Data, not an injector into a flattened UInt. Roughly, the following should be what an InjectorIo is:

sealed class InjectorIo[T <: Data](gen: T) extends Bundle {
  val scan = new ScanIo
  val in = Input(gen)
  val out = Output(gen)
}

This introduces complications into inline compilation as the type that you want to inject into should be some Chisel Data. However, this information is lost at the FIRRTL level. The fault instrumentation annotations can be modified to encode information about the underlying type that will be injected into. Alternatively, the type could be rebuilt from the component. The latter is complicated, but the former is, too. The former requires, I think, the capability to serialize a () => Data function in an annotation.

Rocket Chip Updates

This needs to be updated for the latest version of rocket-chip. The TLBundle* classes no longer have error IO fields.

I applied a quick fix to that, but then I came across a Scala runtime error when trying to build the emulator. The error is a java.lang.reflect.InvocationTargetException caused by:

java.lang.IllegalAccessError: tried to access field freechips.rocketchip.tile.RocketTileModuleImp.reflPoly$Cache4 from class freechips.rocketchip.tile.HasLazyRoCCModule$class
      at freechips.rocketchip.tile.HasLazyRoCCModule$class.reflMethod$Method4(LazyRoCC.scala:91)

Synchronous Reset Error

Hi, I'm just starting to test out chiffre and I was trying to setup the sample LeChiffre configuration. I ended up having to change the patch file, but now I am getting this error and I don't have an idea how to fix it.
Exception in thread "main" java.lang.AssertionError: assertion failed: Error! Synchronous reset should have been removed! UIntType(IntWidth(1)) AsyncResetType
at scala.Predef$.assert(Predef.scala:219)
at firrtl.VerilogEmitter$VerilogRender.regUpdate(Emitter.scala:494)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:647)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1$adapted(Emitter.scala:638)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.ir.Block.foreachStmt(IR.scala:363)
at firrtl.traversals.Foreachers$StmtForMagnet$$anon$1.foreach(Foreachers.scala:18)
at firrtl.traversals.Foreachers$StmtForeach$.foreach$extension(Foreachers.scala:35)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1$adapted(Emitter.scala:638)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.ir.Block.foreachStmt(IR.scala:363)
at firrtl.traversals.Foreachers$StmtForMagnet$$anon$1.foreach(Foreachers.scala:18)
at firrtl.traversals.Foreachers$StmtForeach$.foreach$extension(Foreachers.scala:35)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.$anonfun$build_streams$1$adapted(Emitter.scala:638)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.ir.Block.foreachStmt(IR.scala:363)
at firrtl.traversals.Foreachers$StmtForMagnet$$anon$1.foreach(Foreachers.scala:18)
at firrtl.traversals.Foreachers$StmtForeach$.foreach$extension(Foreachers.scala:35)
at firrtl.VerilogEmitter$VerilogRender.build_streams(Emitter.scala:638)
at firrtl.VerilogEmitter$VerilogRender.emit_verilog(Emitter.scala:838)
at firrtl.VerilogEmitter.$anonfun$emit$3(Emitter.scala:890)
at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:58)
at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:51)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:47)
at firrtl.VerilogEmitter.emit(Emitter.scala:884)
at firrtl.VerilogEmitter.$anonfun$execute$3(Emitter.scala:899)
at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:240)
at scala.collection.immutable.List.foreach(List.scala:388)
at scala.collection.TraversableLike.flatMap(TraversableLike.scala:240)
at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:237)
at scala.collection.immutable.List.flatMap(List.scala:351)
at firrtl.VerilogEmitter.execute(Emitter.scala:896)
at firrtl.Transform.$anonfun$runTransform$2(Compiler.scala:199)
at firrtl.Utils$.time(Utils.scala:186)
at firrtl.Transform.runTransform(Compiler.scala:199)
at firrtl.Compiler.$anonfun$compile$2(Compiler.scala:457)
at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:122)
at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:118)
at scala.collection.immutable.List.foldLeft(List.scala:85)
at firrtl.Compiler.$anonfun$compile$1(Compiler.scala:455)
at firrtl.Utils$.time(Utils.scala:186)
at firrtl.Compiler.compile(Compiler.scala:455)
at firrtl.Compiler.compile$(Compiler.scala:451)
at firrtl.VerilogCompiler.compile(LoweringCompilers.scala:162)
at firrtl.Driver$.$anonfun$execute$1(Driver.scala:241)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:138)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
at logger.Logger$.makeScope(Logger.scala:136)
at firrtl.Driver$.execute(Driver.scala:223)
at firrtl.Driver$.execute(Driver.scala:303)
at firrtl.Driver$.main(Driver.scala:319)
at firrtl.Driver.main(Driver.scala)

Error when try to use Chiffre in a Shifter Register example

I try to apply Chiffre in a shifter register example.

The following attachments are the modified chisel files from Chisel tutorials' file.

Log message:

sbt:chiffre> testOnly examples.ShiftRegisterTester
[info] [0.002] Elaborating design...
[info] [0.173] Done elaborating.
[info] [0.000] Elaborating design...
[deprecated] Lfsr.scala:78 (1 calls): do_apply is deprecated: "Vec(elts) is deprecated, use VecInit(elts) instead"
[warn] There were 1 deprecated function(s) used. These may stop compiling in a future release - you are encouraged to fix these issues.
[warn] Line numbers for deprecations reported by Chisel may be inaccurate; enable scalac compiler deprecation warnings via either of the following methods:
[warn] In the sbt interactive console, enter:
[warn] set scalacOptions in ThisBuild ++= Seq("-unchecked", "-deprecation")
[warn] or, in your build.sbt, add the line:
[warn] scalacOptions := Seq("-unchecked", "-deprecation")
[info] [0.072] Done elaborating.
Total FIRRTL Compile Time: 184.5 ms
Total FIRRTL Compile Time: 942.1 ms
[info] ShiftRegisterTester:
[info] ShiftRegister
[info] - should shift a number through a series of registers in firrtl *** FAILED ***
[info] firrtl.passes.CheckChirrtl$UndeclaredReferenceException: @[:@27.2]: [module ShiftRegister] Reference r0_fault is not declared.
[info] at firrtl.passes.CheckChirrtl$.checkChirrtlE$1(CheckChirrtl.scala:72)
[info] at firrtl.passes.CheckChirrtl$.$anonfun$run$20(CheckChirrtl.scala:101)
[info] at firrtl.ir.DefRegister.mapExpr(IR.scala:224)
[info] at firrtl.Mappers$StmtMagnet$$anon$2.map(Mappers.scala:19)
[info] at firrtl.Mappers$StmtMap$.map$extension(Mappers.scala:33)
[info] at firrtl.passes.CheckChirrtl$.checkChirrtlS$1(CheckChirrtl.scala:101)
[info] at firrtl.passes.CheckChirrtl$.$anonfun$run$22(CheckChirrtl.scala:102)
[info] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:234)
[info] at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:59)
[info] at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:52)
[info] ...
[info] ScalaTest
[info] Run completed in 1 second, 800 milliseconds.
[info] Total number of tests run: 1
[info] Suites: completed 1, aborted 0
[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0
[info] *** 1 TEST FAILED ***

ShiftRegister.zip

Injecting Faults into Member of Aggregate Type

When attempting to inject faults into a (ground) member of an aggregate type, FIRRTL reports an error during one of its passes. For example, if I try to inject an error into the program counter of Rocket Chip, which is defined in IBuf.scala, using:

isFaulty(buf.pc, "main", classOf[inject.StuckAt])

Chiffre reports the following circuit changes:

[info] IBuf
[info]   defines:
[info]     - inst StuckAt of StuckAt
[info]     - wire buf_.pc_fault : UInt<40>
[info]   connects:
[info]     - StuckAt.clock <= clock
[info]     - StuckAt.reset <= reset
[info]     - StuckAt.io.in <= asUInt(buf_.pc)
[info]     - buf_.pc_fault <= asUInt(StuckAt.io.out)
[info]     - StuckAt.io.scan.en is invalid
[info]     - StuckAt.io.scan.clk is invalid
[info]     - StuckAt.io.scan.in is invalid
[info]   modules:
[info]     - StuckAt
[info]   annotations:
[info]     - ScanChainDescriptionAnnotation(ModuleName(StuckAt,CircuitName(StuckAt)),main,StuckAtInjectorInfo(40))
[info]     - SinkAnnotation(ComponentName(StuckAt.io.scan.en,ModuleName(IBuf,CircuitName(TestHarness))),scan_en)
[info]     - SinkAnnotation(ComponentName(StuckAt.io.scan.clk,ModuleName(IBuf,CircuitName(TestHarness))),scan_clk)
[info]     - ScanChainInjectorAnnotation(ComponentName(buf_.pc,ModuleName(IBuf,CircuitName(TestHarness))),main,StuckAt,StuckAt)
[info]     - ScanChainAnnotation(ComponentName(StuckAt.io.scan.in,ModuleName(IBuf,CircuitName(TestHarness))),slave,in,main,Some(ComponentName(buf_.pc,ModuleName(IBuf,CircuitName(TestHarness)))))
[info]     - ScanChainAnnotation(ComponentName(StuckAt.io.scan.out,ModuleName(IBuf,CircuitName(TestHarness))),slave,out,main,Some(ComponentName(buf_.pc,ModuleName(IBuf,CircuitName(TestHarness)))))
[info]   renames:
[info]     - buf_.pc: buf_.pc_fault

But then FIRRTL eventually reports the following error during transform CheckInitialization:

Exception in thread "main" firrtl.passes.CheckInitialization$RefNotInitializedException:  : [module IBuf]  Reference buf_.pc_fault is not fully initialized.
   : buf_.pc_fault <= VOID
        at firrtl.passes.CheckInitialization$$anonfun$firrtl$passes$CheckInitialization$$checkInitM$1$2.apply(CheckInitialization.scala:83)
        at firrtl.passes.CheckInitialization$$anonfun$firrtl$passes$CheckInitialization$$checkInitM$1$2.apply(CheckInitialization.scala:78)
        at scala.collection.TraversableLike$WithFilter$$anonfun$foreach$1.apply(TraversableLike.scala:733)
        at scala.collection.mutable.HashMap$$anonfun$foreach$1.apply(HashMap.scala:130)
        at scala.collection.mutable.HashMap$$anonfun$foreach$1.apply(HashMap.scala:130)
        at scala.collection.mutable.HashTable$class.foreachEntry(HashTable.scala:236)
        at scala.collection.mutable.HashMap.foreachEntry(HashMap.scala:40)
        at scala.collection.mutable.HashMap.foreach(HashMap.scala:130)
        at scala.collection.TraversableLike$WithFilter.foreach(TraversableLike.scala:732)
        at firrtl.passes.CheckInitialization$.firrtl$passes$CheckInitialization$$checkInitM$1(CheckInitialization.scala:78)
        at firrtl.passes.CheckInitialization$$anonfun$run$1.apply(CheckInitialization.scala:89)
        at firrtl.passes.CheckInitialization$$anonfun$run$1.apply(CheckInitialization.scala:88)
        at scala.collection.immutable.List.foreach(List.scala:392)
        at firrtl.passes.CheckInitialization$.run(CheckInitialization.scala:88)
        at firrtl.passes.Pass$class.execute(Passes.scala:24)
        at firrtl.passes.CheckInitialization$.execute(CheckInitialization.scala:17)
        at firrtl.Transform$$anonfun$2.apply(Compiler.scala:257)
        at firrtl.Transform$$anonfun$2.apply(Compiler.scala:257)
        at firrtl.Utils$.time(Utils.scala:182)
        at firrtl.Transform.runTransform(Compiler.scala:257)
        at chiffre.passes.FaultInstrumentationTransform$$anonfun$2.apply(FaultInstrumentationTransform.scala:68)
        at chiffre.passes.FaultInstrumentationTransform$$anonfun$2.apply(FaultInstrumentationTransform.scala:68)
        at scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)
        at scala.collection.immutable.List.foldLeft(List.scala:84)
        at chiffre.passes.FaultInstrumentationTransform.execute(FaultInstrumentationTransform.scala:68)
        at firrtl.Transform$$anonfun$2.apply(Compiler.scala:257)
        at firrtl.Transform$$anonfun$2.apply(Compiler.scala:257)
        at firrtl.Utils$.time(Utils.scala:182)
        at firrtl.Transform.runTransform(Compiler.scala:257)
        at firrtl.Compiler$$anonfun$7$$anonfun$apply$8.apply(Compiler.scala:471)
        at firrtl.Compiler$$anonfun$7$$anonfun$apply$8.apply(Compiler.scala:471)
        at scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)
        at scala.collection.immutable.List.foldLeft(List.scala:84)
        at firrtl.Compiler$$anonfun$7.apply(Compiler.scala:471)
        at firrtl.Compiler$$anonfun$7.apply(Compiler.scala:471)
        at firrtl.Utils$.time(Utils.scala:182)
        at firrtl.Compiler$class.compile(Compiler.scala:470)
        at firrtl.VerilogCompiler.compile(LoweringCompilers.scala:140)
        at firrtl.Driver$$anonfun$execute$1.apply(Driver.scala:226)
        at firrtl.Driver$$anonfun$execute$1.apply(Driver.scala:210)
        at logger.Logger$$anonfun$makeScope$1.apply(Logger.scala:129)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
        at logger.Logger$.makeScope(Logger.scala:127)
        at firrtl.Driver$.execute(Driver.scala:210)
        at firrtl.Driver$.execute(Driver.scala:287)
        at firrtl.Driver$.main(Driver.scala:303)
        at firrtl.Driver.main(Driver.scala)

For some reason, the connection made to buf_.pc_fault that is reported in Chiffre's log output appears to either get erased during one of the later transforms or not actually get created in the first place.

about ScanChainTransform error

Hello, I am very sorry to bother you. I have seen your paper "Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems " and I’m very interested in your Chiffre Fault Injection Framework.

I tried the Chiffer experiment but end up encountering a problem during the configuration of LeChiffre. According to the error log "value is not a member of firrtl.TargetDirAnnotation", I went to check the definition of TargetDirAnnotation in the firrtl source files, but found that the member ‘value’ does not exist.

I see that the FIRRTL project is still being updated. I don't know if it is the reason for the firrtl version to cause this error. I don't know much about the compilation process of firrtl, so I don't have an idea for this problem. I sincerely hope that I can get your help.

The error logs is as follows:
[error] /chiffre/rocket-chip/chiffre/src/main/scala/chiffre/passes/ScanChainTransform.scala:131:95: value value is not a member of firrtl.TargetDirAnnotation
[error] val targetDir = new File(state.annotations.collectFirst{ case a: TargetDirAnnotation => a.value}.getOrElse("."))
[error] ^
[warn] /chiffre/rocket-chip/src/main/scala/util/DescribedSRAM.scala:7:34: imported `Annotated' is permanently hidden by definition of object Annotated in package util
[warn] import freechips.rocketchip.util.Annotated
[warn] ^
[warn] one warning found
[error] one error found

One of the great advantages of Chiffre framework is that it only needs to make few modifications to the original circuit description. Refer to the method of writing chisel and firtrl transforms, I also would like to ask if I want to evaluate my own processor implemented in Chisel language, in addition to the fault injector controller, faulty component and firrtl transforms, what else do I need to do or pay attention to? Do you still have plans for memory fault injection?

Thanks for your time and look forward to your reply.

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