intel-retail/software-vsync-modulation-sample

A SW Library for Digital Signage that provides references on how to modify MMIO PLL registers to slow/speed up VSYNC timings on a system to achieve synchronization. For documentation click on the link below.

software-vsync-modulation-sample's Issues

Only two of the outputs are offering VSync displacement

Included in a LOG for a 3x1 configuration using HMDI only. Only two of the outputs are offering VSync displacement.

The HDMI-3 and DP-1 connectors look ok (I will confirm tomorrow).

Note. The configuration 2x1 also has VSync displacement not working in certain conditions.

Display Properties. (3, 1) :: (HDMI-1, HDMI-3) :: primary+secondary OK
Display Properties. (2, 1) :: (HDMI-2, HDMI-3) :: secondary OK (missing COMBO/cfgcr0)
Display Properties. (3, 2) :: (HDMI-1, HDMI-2) :: primary+secondary OK
Display Properties. (1, 2) :: (HDMI-3, HDMI-2) :: secondary OK (missing COMBO/cfgcr0)

Display Setting (3, 2, 1) (HDMI-1, HDMI-2, HDMI-3)

The VSync gets modified for monitor 1 and 3.

$ xrandr
Screen 0: minimum 320 x 200, current 11520 x 2160, maximum 16384 x 16384
DP-1 disconnected (normal left inverted right x axis y axis)
HDMI-1 connected primary 3840x2160+0+0 (normal left inverted right x axis y axis) 597mm x 336mm
HDMI-2 connected 3840x2160+3840+0 (normal left inverted right x axis y axis) 597mm x 336mm
HDMI-3 connected 3840x2160+7680+0 (normal left inverted right x axis y axis) 597mm x 336mm

DP-2 disconnected (normal left inverted right x axis y axis)

$ sudo LD_LIBRARY_PATH=/temp/new ./new/synctest
[DBG] Device id is 0x46A8
[DBG] DKL phy #2 is on
[DBG] Total DKL phys on: 1
[DBG] steps are 1000
[DBG] OLD VALUES
dkl_pll_div0        0x7E284274
dkl_visa_serializer           0x54321000
dkl_bias               0xC1000000
dkl_ssc                  0x400020FF
dkl_dco                0xE4004080
[DBG] old pll_freq             8910.000000
[DBG] new_pll_freq         8918.910000
[DBG] new fbdivfrac         0x86CCC
[DBG] NEW VALUES
dkl_pll_div0        0x7E284274
dkl_visa_serializer           0x54321200
dkl_bias               0xC86CCC00
dkl_ssc                  0x400020FF
dkl_dco                0xE4004084
[DBG] timer done
[DBG] DEFAULT VALUES
dkl_pll_div0        0x7E284274
dkl_visa_serializer           0x54321000
dkl_bias               0xC1000000
dkl_ssc                  0x400020FF
dkl_dco                0xE4004080
[DBG] 0x60400 = 0x90030011
[DBG] ddi_select = 0x2
[DBG] 0x164280 = 0x1E01400
[DBG] DPLL num = 0x0
[DBG] 0x61400 = 0xA8030011
[DBG] ddi_select = 0x5
[DBG] 0x62400 = 0xB0030011
[DBG] ddi_select = 0x6
[DBG] 0x63400 = 0x30000
[DBG] Pipe 4 is turned off
[DBG] DPLL 0 is enabled with a Combo phy
[DBG] Total Combo phys on: 1
[DBG] steps are 1000
[DBG] OLD VALUES
cfgcr0    0x1001D0
cfgcr1    0x448
OLD VALUES
cfgcr0    0x1001D0
cfgcr1    0x448
[DBG] old pll_freq             594.000000
[DBG] new_pll_freq         594.594000
[DBG] old dco_clock         8910.000000
[DBG] new dco_clock       8918.910000
[DBG] old fbdivfrac           0x400
[DBG] old ro_div_frac      0x8000
[DBG] old fbdivint             0x1D0
[DBG] old ro_div_int        0x3A
[DBG] new fbdivfrac         0x21B3
[DBG] new ro_div_frac  0x43666
[DBG] NEW VALUES
cfgcr0    0x86CDD0
NEW VALUES
cfgcr0    0x86CDD0
[DBG] timer done
[DBG] DEFAULT VALUES
cfgcr0    0x1001D0
cfgcr1    0x448

Update Documentation to include check for PTP Support

ethtool -T

Raptor Lake Not Supported

Device IDs for RPL missing and platform not validated:

qdiv (and pll_freq) generate a divide by 0

-when using a 4x1 configuration , the computations for qdiv (and pll_freq) generate a divide by 0.

/* TODO: In case we run into some other weird dividers, then we may need to revisit this */
int qdiv = (kdiv == 2) ? GETBITS_VAL(combo_table[i].cfgcr1.orig_val, 17, 10) : 1;

int ro_div_bias_frac = i_fbdivfrac_14_0 << 5 | ((i_fbdiv_intgr_9_0 & GENMASK(2, 0)) << 19);
int ro_div_bias_int = i_fbdiv_intgr_9_0 >> 3;
double dco_divider = 4*((double) ro_div_bias_int + ((double) ro_div_bias_frac / pow(2,22)));
double dco_clock = 2 * REF_COMBO_FREQ * dco_divider;
double pll_freq = dco_clock / (5 * pdiv * qdiv * kdiv);
double new_pll_freq = pll_freq + (shift * pll_freq / 100);

OLD VALUES
cfgcr0    0xE001A5
cfgcr1    0x88
old pll_freq         inf 
new_pll_freq     inf 
old dco_clock      8100.000000
new dco_clock    8108.100000

Shared PLL causes inability to sync

There is a single PLL for a pair of outputs that have misaligned V-Blank. Need a way to control all 4 outputs separately with 4 PLLs. Or if several outputs are controlled by a single PLL, we need a way to have their V-Blank aligned

Disable secure boot

Add prerequisite to disable secure boot, otherwise the register writes will fail