j-marjanovic/pp-sp-reference-design

Unofficial Pikes Peak/Storey Peak reference design

Software generation

Here are the commands which were used to generate software project. Maybe this can be useful when setting up single-script build for CI.

Generate BSP

nios2-bsp hal . ../../qsys/system.sopcinfo --cpu-name nios2_gen2_0 --type-version 16.1

Generate application

nios2-app-generate-makefile --app-dir . --bsp-dir ../otma_bringup_bsp --elf-name

pp-sp-reference-design's Issues

IDT clock generator pinouts

I understand from the constraints that the PIN_N7 is IDT I2C Clock and PIN_P7 is I2C Data and pins T7 and T6 are the differential clock outputs (Q and nQ).

How did you managed to program and select the frequency using FSEL and OE pins? Are they the REDCLK0 to 4 that are in the constraints file?

Illegal routes

I am using Quartus 18.0
I did successfully generated bitstream, I used https://gist.github.com/wirebond/9e75db58112bb49c6b2debad7dc13cb2 to enable second HIP and I can see it used in Chip Planer.

Everything seems fine however there are two routes with status illegal.

inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|clocktopld	inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|clocktopld	Generated	Illegal
inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|observablebyteserdesclock	inst_system|pcie1|altera_s5_a2p|altpcie_hip_256_pipen1b|g_xcvr.sv_xcvr_pipe_native|inst_sv_xcvr_native|inst_sv_pcs|ch[4].inst_sv_pcs_ch|inst_sv_hssi_8g_rx_pcs|wys|observablebyteserdesclock	Generated	Illegal

Is this expected?

Template for the PCIe IO constraints

Looking at the traces, looks like the board has all x16 lanes. Looking at Occamlab (http://virtlab.occamlab.com/home/zapisnik/microsoft-catapult-v2) pinouts, I added to a constraints template the transceivers used on it (not sure about the order). It might be able to infer the pins by using https://github.com/j-marjanovic/otma-pin-re/blob/38520103abc0f5ef7f48ba0bc93cb4620af87055/resources/5sgsd5.txt if you think it is correct (based on transceiver).

Here is the template:

# PCIe x16
set_location_assignment PIN_ -to XCVR_PCIE_TX[0]     ;#GXB_TX_R0p
set_location_assignment PIN_ -to XCVR_PCIE_TX[1]     ;#GXB_TX_R1p
set_location_assignment PIN_ -to XCVR_PCIE_TX[2]     ;#GXB_TX_R2p
set_location_assignment PIN_ -to XCVR_PCIE_TX[3]     ;#GXB_TX_R3p
set_location_assignment PIN_ -to XCVR_PCIE_TX[4]     ;#GXB_TX_R5p
set_location_assignment PIN_ -to XCVR_PCIE_TX[5]     ;#GXB_TX_R6p
set_location_assignment PIN_ -to XCVR_PCIE_TX[6]     ;#GXB_TX_R7p
set_location_assignment PIN_ -to XCVR_PCIE_TX[7]     ;#GXB_TX_R8p
set_location_assignment PIN_ -to XCVR_PCIE_TX[8]     ;#GXB_TX_L0p
set_location_assignment PIN_ -to XCVR_PCIE_TX[9]     ;#GXB_TX_L1p
set_location_assignment PIN_ -to XCVR_PCIE_TX[10]    ;#GXB_TX_L2p
set_location_assignment PIN_ -to XCVR_PCIE_TX[11]    ;#GXB_TX_L3p
set_location_assignment PIN_ -to XCVR_PCIE_TX[12]    ;#GXB_TX_L5p
set_location_assignment PIN_ -to XCVR_PCIE_TX[13]    ;#GXB_TX_L6p
set_location_assignment PIN_ -to XCVR_PCIE_TX[14]    ;#GXB_TX_L7p
set_location_assignment PIN_ -to XCVR_PCIE_TX[15]    ;#GXB_TX_L8p
set_location_assignment PIN_ -to XCVR_PCIE_RX[0]     ;#GXB_RX_R0p
set_location_assignment PIN_ -to XCVR_PCIE_RX[1]     ;#GXB_RX_R1p
set_location_assignment PIN_ -to XCVR_PCIE_RX[2]     ;#GXB_RX_R2p
set_location_assignment PIN_ -to XCVR_PCIE_RX[3]     ;#GXB_RX_R3p
set_location_assignment PIN_ -to XCVR_PCIE_RX[4]     ;#GXB_RX_R5p
set_location_assignment PIN_ -to XCVR_PCIE_RX[5]     ;#GXB_RX_R6p
set_location_assignment PIN_ -to XCVR_PCIE_RX[6]     ;#GXB_RX_R7p
set_location_assignment PIN_ -to XCVR_PCIE_RX[7]     ;#GXB_RX_R8p
set_location_assignment PIN_ -to XCVR_PCIE_RX[8]     ;#GXB_RX_L0p
set_location_assignment PIN_ -to XCVR_PCIE_RX[9]     ;#GXB_RX_L1p
set_location_assignment PIN_ -to XCVR_PCIE_RX[10]    ;#GXB_RX_L2p
set_location_assignment PIN_ -to XCVR_PCIE_RX[11]    ;#GXB_RX_L3p
set_location_assignment PIN_ -to XCVR_PCIE_RX[12]    ;#GXB_RX_L5p
set_location_assignment PIN_ -to XCVR_PCIE_RX[13]    ;#GXB_RX_L6p
set_location_assignment PIN_ -to XCVR_PCIE_RX[14]    ;#GXB_RX_L7p
set_location_assignment PIN_ -to XCVR_PCIE_RX[15]    ;#GXB_RX_L8p

set_location_assignment PIN_ -to "XCVR_PCIE_TX[0](n)"     ;#GXB_TX_R0n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[1](n)"     ;#GXB_TX_R1n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[2](n)"     ;#GXB_TX_R2n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[3](n)"     ;#GXB_TX_R3n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[4](n)"     ;#GXB_TX_R5n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[5](n)"     ;#GXB_TX_R6n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[6](n)"     ;#GXB_TX_R7n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[7](n)"     ;#GXB_TX_R8n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[8](n)"     ;#GXB_TX_L0n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[9](n)"     ;#GXB_TX_L1n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[10](n)"    ;#GXB_TX_L2n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[11](n)"    ;#GXB_TX_L3n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[12](n)"    ;#GXB_TX_L5n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[13](n)"    ;#GXB_TX_L6n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[14](n)"    ;#GXB_TX_L7n
set_location_assignment PIN_ -to "XCVR_PCIE_TX[15](n)"    ;#GXB_TX_L8n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[0](n)"     ;#GXB_RX_R0n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[1](n)"     ;#GXB_RX_R1n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[2](n)"     ;#GXB_RX_R2n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[3](n)"     ;#GXB_RX_R3n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[4](n)"     ;#GXB_RX_R5n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[5](n)"     ;#GXB_RX_R6n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[6](n)"     ;#GXB_RX_R7n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[7](n)"     ;#GXB_RX_R8n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[8](n)"     ;#GXB_RX_L0n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[9](n)"     ;#GXB_RX_L1n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[10](n)"    ;#GXB_RX_L2n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[11](n)"    ;#GXB_RX_L3n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[12](n)"    ;#GXB_RX_L5n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[13](n)"    ;#GXB_RX_L6n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[14](n)"    ;#GXB_RX_L7n
set_location_assignment PIN_ -to "XCVR_PCIE_RX[15](n)"    ;#GXB_RX_L8n

set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[4]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[5]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[6]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[7]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[8]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[9]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[10]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[11]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[12]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[13]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[14]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_TX[15]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[4]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[5]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[6]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[7]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[8]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[9]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[10]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[11]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[12]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[13]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[14]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to XCVR_PCIE_RX[15]

## PCIe Clock and SMB
set_location_assignment PIN_ -to XCVR_PCIE_CLK
set_location_assignment PIN_ -to "XCVR_PCIE_CLK(n)"
set_location_assignment PIN_ -to PCIE_SMBCLK
set_location_assignment PIN_ -to PCIE_SMBDAT
set_location_assignment PIN_ -to PCIE_WAKEN_R
set_location_assignment PIN_ -to PCIE_PERSTN

set_instance_assignment -name IO_STANDARD "HCSL" -to XCVR_PCIE_CLK
set_instance_assignment -name IO_STANDARD "LVTTL" -to PCIE_SMBCLK
set_instance_assignment -name IO_STANDARD "LVTTL" -to PCIE_SMBDAT
set_instance_assignment -name IO_STANDARD "LVTTL" -to PCIE_WAKEN_R
set_instance_assignment -name IO_STANDARD "LVTTL" -to PCIE_PERSTN

Also I don't know the IO stantard, I based on another Terasic board that uses same FPGA and has PCIe. Don't know if my logic is correct.

Added I2C temperature sensors and missing pin on QSFP

Looking at some documentation from http://virtlab.occamlab.com/home/zapisnik/microsoft-catapult-v2 and your dump on https://github.com/j-marjanovic/otma-pin-re/blob/38520103abc0f5ef7f48ba0bc93cb4620af87055/resources/5sgsd5.txt, I figured out the Temp monitoring over I2C pins for the IO constraints file:

# Remote and Local Temperature Sensor I2C
set_location_assignment PIN_AW26 -to I2C_MON_SCL
set_location_assignment PIN_AV26 -to I2C_MON_SDA
set_instance_assignment -name IO_STANDARD "2.5 V" -to I2C_MON_SCL
set_instance_assignment -name IO_STANDARD "2.5 V" -to I2C_MON_SDA
set_instance_assignment -name SLEW_RATE 0 -to I2C_MON_SCL
set_instance_assignment -name SLEW_RATE 0 -to I2C_MON_SDA
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to I2C_MON_SCL
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to I2C_MON_SDA

Also saw that the QSFP cage 1 missed a pin, RX[3] as:

set_location_assignment PIN_M1 -to "XCVR_QSFP0_RX[3](n)"     ;#GXB_RX_R13n

I added the transceivers used on them as fetched from Occamlab:

# QSFP 0
set_location_assignment PIN_U4 -to XCVR_QSFP0_TX[0]     ;#GXB_TX_R10p
set_location_assignment PIN_R4 -to XCVR_QSFP0_TX[1]     ;#GXB_TX_R11p
set_location_assignment PIN_N4 -to XCVR_QSFP0_TX[2]     ;#GXB_TX_R12p
set_location_assignment PIN_L4 -to XCVR_QSFP0_TX[3]     ;#GXB_TX_R13p
set_location_assignment PIN_V2 -to XCVR_QSFP0_RX[0]     ;#GXB_RX_R10p
set_location_assignment PIN_T2 -to XCVR_QSFP0_RX[1]     ;#GXB_RX_R11p
set_location_assignment PIN_P2 -to XCVR_QSFP0_RX[2]     ;#GXB_RX_R12p
set_location_assignment PIN_M2 -to XCVR_QSFP0_RX[3]     ;#GXB_RX_R13p

set_location_assignment PIN_U3 -to "XCVR_QSFP0_TX[0](n)"     ;#GXB_TX_R10n
set_location_assignment PIN_R3 -to "XCVR_QSFP0_TX[1](n)"     ;#GXB_TX_R11n
set_location_assignment PIN_N3 -to "XCVR_QSFP0_TX[2](n)"     ;#GXB_TX_R12n
set_location_assignment PIN_L3 -to "XCVR_QSFP0_TX[3](n)"     ;#GXB_TX_R13n
set_location_assignment PIN_V1 -to "XCVR_QSFP0_RX[0](n)"     ;#GXB_RX_R10n
set_location_assignment PIN_T1 -to "XCVR_QSFP0_RX[1](n)"     ;#GXB_RX_R11n
set_location_assignment PIN_P1 -to "XCVR_QSFP0_RX[2](n)"     ;#GXB_RX_R12n
set_location_assignment PIN_M1 -to "XCVR_QSFP0_RX[3](n)"     ;#GXB_RX_R13n

set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_TX[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_TX[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_TX[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_TX[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_RX[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_RX[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_RX[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP0_RX[3]

# QSFP 1
set_location_assignment PIN_J4 -to XCVR_QSFP1_TX[0]     ;#GXB_TX_R14p
set_location_assignment PIN_G4 -to XCVR_QSFP1_TX[1]     ;#GXB_TX_R15p
set_location_assignment PIN_E4 -to XCVR_QSFP1_TX[2]     ;#GXB_TX_R16p
set_location_assignment PIN_C4 -to XCVR_QSFP1_TX[3]     ;#GXB_TX_R17p
set_location_assignment PIN_K2 -to XCVR_QSFP1_RX[0]     ;#GXB_RX_R14p
set_location_assignment PIN_H2 -to XCVR_QSFP1_RX[1]     ;#GXB_RX_R15p
set_location_assignment PIN_F2 -to XCVR_QSFP1_RX[2]     ;#GXB_RX_R16p
set_location_assignment PIN_D2 -to XCVR_QSFP1_RX[3]     ;#GXB_RX_R17p

set_location_assignment PIN_J3 -to "XCVR_QSFP1_TX[0](n)"     ;#GXB_TX_R14n
set_location_assignment PIN_G3 -to "XCVR_QSFP1_TX[1](n)"     ;#GXB_TX_R15n
set_location_assignment PIN_E3 -to "XCVR_QSFP1_TX[2](n)"     ;#GXB_TX_R16n
set_location_assignment PIN_C3 -to "XCVR_QSFP1_TX[3](n)"     ;#GXB_TX_R17n
set_location_assignment PIN_K1 -to "XCVR_QSFP1_RX[0](n)"     ;#GXB_RX_R14n
set_location_assignment PIN_H1 -to "XCVR_QSFP1_RX[1](n)"     ;#GXB_RX_R15n
set_location_assignment PIN_F1 -to "XCVR_QSFP1_RX[2](n)"     ;#GXB_RX_R16n
set_location_assignment PIN_D1 -to "XCVR_QSFP1_RX[3](n)"     ;#GXB_RX_R17n

set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_RX[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_RX[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_RX[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_RX[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_TX[3]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_TX[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_TX[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to XCVR_QSFP1_TX[0]

I haven't validated it on the board but it's consistent to both findings.

Library setup for quartus project

Hi Jan,
thanks for the great project.
I just tried reproducing it locally and ran into missing component issues:
Warning (125092): Tcl Script File ../qsys/system/synthesis/system.qip not found
And then during compilation:
Error (12006): Node instance "inst_system" instantiates undefined entity "system". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

Therefore I went back to the blinky example which worked as expected. 🥳
When I update to your second commit I run into this issue:
Error (12252): System.clock_counter_0: Component clock_counter 1.0 not found or could not be instantiated

I'm assuming that all of these errors are related to my local library setup not being configured properly.
So far all I did was take your project and open it with quartus.
This is probably a very easy question but I have been mainly using Vivado and Yosys so I'm not super familiar with quartus.
Best wishes
Martin