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This is an experiment for lab's members, aiming to design an RV32 SoC. In the future, we will continuously add the desired functions to it.

License: MIT License

SystemVerilog 59.59% Verilog 40.41%

panxi-rv32core's Introduction

PANXI-RV32

This is an experiment for lab's members, aiming to design an RV32 SoC. In the future, we will continuously add the desired functions to it.

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PANXI-RV32

A "perfect" readme document for you to start the project!
Explore the documentation of this project. »

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Contents

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├── /ReadMe-deps/
├── LICENSE
└── README.md

Version Control

This project uses Git for version control. You can check the available versions in the repository.

Author

@ Microelectronics R&D Center in Shanghai University

You can also check the list of contributors to see all the developers involved in this repo.

License

This project is licensed under the MIT License. For details, please refer to the LICENSE file.

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