A RISC microprocessor architecture
This repository contains the epRISC ISA, a reference implementation, and sample code.
epRISC is a 32-bit RISC microprocessor architecture. It is designed to be easy to program for and easy to implement.
Check out documentation/isa_v5 for more information on the architecture itself.
The reference impementation has modules for an SDRAM controller, a text-mode video card, a three-wire UART, SPI, and a fast parallel bus called sysX (which is very similar to Quad SPI). These modules are mostly working as of today and will synthesize without much trouble on Altera MAX 10 devices.
The reference impementation also has epRISC code for driving all of these modules, a ROM with helper routines for things like strings and SD cards, and a machine-level monitor application. There is preliminary work being done on a Forth interpreter as well.
Go fetch some more repos:
spasm is the assembler.
flail is the emulator.
snag is the development board it runs on.
The assembler is reasonably complete and bug-free, and there are plenty of commented examples of epRISC programs in the software directory (although no formal spec sheet yet). The emulator is still being developed, but will work for testing most programs that don't rely on any hardware but the serial port.
The development board is working, but I wouldn't recommend trying to build your own just yet. There's a fair number of mistakes and missteps that need correcting first.
For the time being, you might want to clone this repository instead. I've only just started moving things to separate repositories and there are bound to be issues with uncorrected file paths.
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