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Yu-Sheng Lin's Projects

cocotb icon cocotb

Coroutine Co-simulation Test Bench

cppman icon cppman

C++ 98/11/14 manual pages for Linux/MacOS

memhierbench icon memhierbench

An approach for reproducing the AIDA64 benchmark using C++.

namedtuple icon namedtuple

Implementation of super-fast C++-styled namedtuple, for compile-time reflection.

nicotb icon nicotb

A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.

openlane icon openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

ramulator icon ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

sysbench icon sysbench

Scriptable database and system performance benchmark

umi icon umi

This project implements the paper "Unrolled Memory Inner-Products: An Abstract GPU Operator for Efficient Vision-Related Computations" (ICCV 2017).

verilator icon verilator

Verilator open-source SystemVerilog simulator and lint system

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