After completing the Verilog files, use Modelsim to verify them, the Command-Line Modelsim is recommended.
wsrun.pl <name of your testbench module> <testbench file name> <list of verilog files>
-
Copy two class files
Vcheck.class
andVerFile.class
into the directory folder -
Run
vcheck-all.sh
command in the directory
- untar using tar -xvzf command
tar -xvf filename.tgz
- compress using tar -cvzf command
tar -cvzf filename.tgz filename/
- Script Checker
/u/s/i/sinclair/public/html/courses/cs552/spring2022/handouts/scripts/project/phase1/verify_submission_format.sh filename.tgz
- Python Checker
python3 /u/s/i/sinclair/public/html/courses/cs552/spring2022/handouts/scripts/hw1/verify_submission_format.py filename.tgz
Professor Matt Sinclair @ UW-Madison, Instrutor of ECE/CS 552 - Spring 2022