buffermapping's Issues
Update of Address Pattern
- Shall we add an invalid cycle like atherling?
- Add a state for quasi-affine access pattern if we are doing division and round.
arbitrary address mode is broken
Reading any address in the arbitrary_addr/manual_switch mode returns 1 regardless of the address passed in.
Coding Issue
- Linking C++ Functional Model with the Python Class
- Use PyBinding to link the
cfunc
of unified buffer with the python rewrite rule unified buffer class. Currently they are separate. - Use PyCoreIR instead of parsing the json file.
- Reference to how aetherling did this.
New Rewrite Rules
- Storage Flatten with more complex access pattern, for example, sram in the new memtile architecture.
- Banking strategy with block, cyclic.
Valid signal of line buffer when last level is not a register
When the last level of a line buffer is not a register (such as in multichannel convolution), there are multiple valid signals connected to self.valid
:
Error Validating def
ERROR: Cannot connect multiple outputs to an inputs
In Module: DesignTop
self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_1.valid
self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_0_1.valid
self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_1_1.valid
self.valid : BitIn <== ub_hw_input_stencil_update_streamlinebuffer_bank_0_2_1.valid
self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_1.valid
self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_0_1.valid
self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_1_1.valid
self.valid : BitIn <== ub_kernel_streamlinebuffer_bank_0_2_1.valid
Example is from 16x16x32 3x3 convolution.
CoreIR Unified Buffer shared object File name change
Change libfuncubuf.so
to libcoreir-lakelib.so
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