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View Code? Open in Web Editor NEWA New Programming Language for FPGA Projects
Home Page: https://sourceforge.net/p/alcha/wiki
License: GNU General Public License v3.0
A New Programming Language for FPGA Projects
Home Page: https://sourceforge.net/p/alcha/wiki
License: GNU General Public License v3.0
Once the thesis is complete, phoenix the compiler architecture so that the built-in data structures, data flow and overall concept follows the design presented in the thesis.
The thesis also introduces new features (nested attribute dictionaries, stream-lined translation phases, "this" reference within classes, etc.), all of which require major rework on the compiler.
For compiler: look at MD5 sum, not the modification date.
When the comment closes as "+/+/", the comment region is not ended. Putting a space "+/ +/" hides the symptom.
Keep import AST in a BST and parse the file only once.
Just after parsing to AST, simplify the AST as far as possible?
Alcha must support the concept of "virtual" pins. If a pin does not specify a location, it's automatically marked as virtual (turned into a net in Xilinx (which does not support virtual pins), and marked as a virtual pin in the QSF in Altera).
Once the thesis is complete, transfer the thesis version of the EBNF and language specification to the Wiki.
The first comment of the file is associated with the file (it is the header).
Any other comment is associated with the next expression (or structure).
Make this part of the parser. The comments must follow all the way to the final output.
There has been some major updates to the EBNF. The parser needs to be brought in line.
Comments that start with !! must be printed out to the command-line while the compilation is in progress...
This can be used for To-Do messages, etc...
Scripts must be evaluated only when required:
Abstract the time between signals so that Alcha automatically generate the counters, etc. for something like the timing generator.
Object attributs should allow location constraints, so that a module instance (class instance) can be constrained to a fixed region of the FPGA fabric.
Another application is to constrain a PLL to a specific resource, as is required for the MAX10 ADC PLL.
Instead of __DATE__
and __TIME__
strings, make them numerical instead...
Or perhaps have __YEAR__
, __MONTH__
, etc. as num
type...
The current scanner assumes that U+200C and U+200D are spaces, where they are actually joiners and should not be handled as spaces.
The Unicode standard specifically states that U+2060 must be ignored for "word segmentation".
Similar with U+180E. The standard states that "MVS is not a suffix but an integral part of
the word stem"
The compiler should produce LaTeX / HTML-based reports on:
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