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I am professional baseband system engineer in Dresden, Germany. I am mostly interested on designing and deploying versatile and agile state-of-the-art compute platforms for wireless communication systems. I am currently working on bringing hardware acceleration to the Radio Access Network (RAN), while integrating it with the Core Network.

Motto

It is better to die on your feet that live on your knees - Emiliano Zapata.

Main functional motivation

Hardware-Software Co-Design of the entire product development life cycle for 5G's RAN and Core Network.

Contact

You can contact me mainly via E-mail under the following address or Twitter account.

Current projects

In this moement, we are working on two different projects about wireless communications and genetics.

  1. Hardware accelerated version of the Open RAN Intelligent Controller (RIC).
  2. Hardware accelerated version of the training sequence for protein folding. ESM Meta

Javier Acevedo's Projects

hydroponic_agriculture_learning icon hydroponic_agriculture_learning

This respository contains the source code for the Hydrophonic Agriculture Learning project for the Climate Change Challenge from SensiML and QuickLogic. Either Hardware and Software repositories cointain Board Support Packages.

jracevedob icon jracevedob

This is a personal website where you can find research, entrepenerial projects, vast language support, while having fun.

jupyter-racinecarree icon jupyter-racinecarree

This directory contains the development in Jupyter of the Racine Carrée project - Französisches Insitut Dresden

mpsoc_networking icon mpsoc_networking

This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)

operan icon operan

This repository contains the two different algorithms to synchronize the data path of the up- and downlink of 5G Radio Access Networks

orchestran icon orchestran

This repository contains the findings for scheduling heterogeneous payloads within the Distributed Unit (DU) of a 5G Radio Access Network (RAN)

post-shannon-sdr icon post-shannon-sdr

In this repository, you will find the source code for analyzing tracks during data transmission using Software Defined Radios. Metrics about error positioning and error syndrome are attached.

processor-design icon processor-design

In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.

protein-decomposition icon protein-decomposition

This repository contains the implementation of hardware accelerators for the computing of protein decomposition.

pspin icon pspin

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

pynq icon pynq

Python Productivity for ZYNQ

ricci icon ricci

This repository contains the source code for the RICCI project. RICCI represents a new and revolutionary way of understanding fashion and its role as a social driving force. By introducing automatic robot teaching concepts instead of antiquate and inconvenient robot programming, we pretend to set a new forms of human machine interactions.

rlnc_mpsoc icon rlnc_mpsoc

This directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.

ros-automatic-code-gen icon ros-automatic-code-gen

In this repository, you will find the source code for generation of hardware accelerators on-the-fly for ROS nodes

rust icon rust

Empowering everyone to build reliable and efficient software.

rust-vmm-container icon rust-vmm-container

Container with all dependencies required for running rust-vmm crates integration tests.

scripting icon scripting

In this repository, you will find different examples of shell-based scripting to execute different task ranging from automatic code generation for MPSoC to web browser manipulation.

sympy icon sympy

A computer algebra system written in pure Python

thefifthdriverai icon thefifthdriverai

The Fifth Driver is a project for the Adaptative Computing Developer Contest for Xilinx. We pretend to demonstrate that the Xilinx Ultrascale+ MPSoC architecture is suitable for developing machine learning applications applied to Autonomous Driving.

ucx icon ucx

Unified Communication X (mailing list - https://elist.ornl.gov/mailman/listinfo/ucx-group)

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