krishna-beemanapalli/6tsram

layout-simulation-comparison

6TSRAM

layout-simulation-comparison

== Description ==

The project contains the layout of a 6-transistor SRAM, created using electric. The layout is exported to SPICE and simulated for read/write operations using Xyce. The area of custom SRAM is compared to the SRAM generated by OpenRAM

== Layout ==

The layout can be opened using the electric software included, make sure you have java runtime environment installed. Height of cell = 54x25nmx10-3 = 1.35um Width of cell = 54x25nmx10-3 = 1.35um Total area = 1.35um x 1.35um = 1.8225um2

== Simulation ==

The layout is exported into SPICE and simulated for correctness. The read and write SPICE files are included for simulation, the parameters for the MOSFETs is imported from the High Performance 45nm file.

== Comparison ==

Source Code and instructions to use OpenRAM can be obtained from https://github.com/VLSIDA/OpenRAM Customize the mem.py to your memory size for generating memory. (.lef, .lib, .sp, .v, etc) will be generated and from there you can get total area.