lavender2000/vhdl-clock-project

⏰ A Fully Functional Clock with alarm and snooze .

VHDL-Clock-Project

This project is a part of Koc University Elec204 lecture.

To design a timer (HH:MM:SS, H: hours, M: minutes, S: seconds), which can be operated in SET, RESET and READ modes.First designed a new clock generator, which generates a 1 Hz clock (a rising edge every second). Then, designed a functional block, which takes the necessary inputs for mode selection and inputs for setting the timer digits and finally display the time on the 7-segment displays.

The purpose of this project is to use combinational and sequential logic circuit design principles to design a timer with three different modes. Other forms of timers, such as down-counting timers, millisecond or microsecond timers, can be later designed as needed after this project based on the requirements and specifications of a given project.