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View Code? Open in Web Editor NEWMOS 6581/8580 SID schematics reverse-engineered
MOS 6581/8580 SID schematics reverse-engineered
Reverse-engineering of the MOS 6581/8580 SID schematics by Leandro Nini and ttlworks, based on silicon layouts photographed by Michael Huth and revectorized and annotated by Tommi Lempinen. https://github.com/libsidplayfp/SID_schematics/wiki Original DIE pictures by Michael Huth: https://retronn.de/imports/commodore_chips.html (old page: http://mail.lipsia.de/~enigma/neu/6581.html) Original layouts by Tommi Lempinen: http://oms.wmhost.com/misc/ Discussion: http://forum.6502.org/viewtopic.php?f=8&t=4150 Diagrams made with Dia: https://wiki.gnome.org/Apps/Dia
If PDET2 is delayed by one cycle, and pot_cnt_n are not, I cannot see how the paddle circuit can work.
Are by any chance all pot_cnt_n also delayed by one cycle? Or is there something I didn't understand correctly?
While the old page is still available I don't update anything there anymore.
The current page is:
https://retronn.de/imports/commodore_chips.html
The new server should also be a bit faster.
Working on https://github.com/daglem/reDIP-SID, I noticed a small error in the schematic for the envelope counter.
See the attached image for where I believe the gate signal should be inverted.
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