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大三上小学期的硬件综合设计

Tcl 0.04% Verilog 14.64% VHDL 71.10% C 0.43% SystemVerilog 0.21% Pascal 0.01% Makefile 0.01% Assembly 11.95% C++ 0.03% V 1.28% Shell 0.21% Stata 0.03% Forth 0.01% JavaScript 0.05% Batchfile 0.01% HTML 0.01% PureBasic 0.01%

hardware-design's Introduction

hardware-design

大三上小学期的硬件综合设计

参考说明


  1. "自己动手写CPU/自己动手写CPU光盘资源.rar"
  2. MIPS-CPU-implementation
  3. 硬件综合设计资料_full_v0.1.zip
  4. cqu设计要求以及文档地址gitee

一些目录说明


  1. axi, axi连线以及cache的功能测试。

  2. cpu132_gettrace, goden_trace文件所在目录(soc_sram_func\testbench\mycpu_tb.v要用到)

  3. perf_test_v0.01,通过axi+cache(写直达)的性能测试。

  4. soc_sram_func,实现了57条指令的openmips

    4.1 工程目录

    soc_sram_func/run_vivado/mycpu_prj1/mycpu.xpr"

    4.2 源代码

    soc_sram_func/rtl/myCPU

  5. soft, 里面是测试指令目录

  6. test_on_site, 现场添加指令说明。

  7. 测试流程,这次小学期中自己动手写cpu到底该如何进行的说明。

  8. 实验结果, 最终结果记录。

  9. 自己动手写cpu,来源于 《自己动手写CPU》.(雷思磊)。

  10. cache_lab_v0.06.zip 计算机体系结构实验二所发的源码(需要自己实现写回cache)

  11. shiyan4.zip,计算机组成原理实验4(流水线,十条指令)。

  12. 硬综设计资料_full_v0.1.zip,cqu设计要求以及文档地址gitee中的资料。

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