Error in Simple system VCS+Verdi simulation, Failed to find the Verdi database

[tju-sun-lab]

Error in Simple system VCS+Verdi simulation, Failed to find the Verdi database

[tju-sun-lab]

I modified the "ibex_simple_system.core" file and added a "-kdb" option, then the problem seems to be solved.
The sim section in the file will be

sim:
<<: *default_target
default_tool: verilator
tools:
vcs:
vcs_options:
- '-xlrm uniq_prior_final'
- '-debug_access+r'
- '-kdb'
verilator:
mode: cc
verilator_options:
# Disabling tracing reduces compile times but doesn't have a
# huge influence on runtime performance.
- '--trace'
- '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
- '--trace-structs'
- '--trace-params'
- '--trace-max-array 1024'
- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- "-Wall"
- "-Wwarn-IMPERFECTSCH"
# RAM primitives wider than 64bit (required for ECC) fail to build in
# Verilator without increasing the unroll count (see Verilator#1266)
- "--unroll-count 72"

[rswarbrick]

This looks like a sensible change to me. (And the VCS support in that file was written by me, back in 2020!)

Are you happy to open a PR with it?

[tju-sun-lab]

This looks like a sensible change to me. (And the VCS support in that file was written by me, back in 2020!)

Are you happy to open a PR with it?

Happy to that! I will open a pull request asap.