If instr[14:12]=3’b111”, rd=M[rs1+rs2]. This instruction code is not defined in the RISC-V spec.

[lowrisc]

If instr[14:12]=3’b111”, rd=M[rs1+rs2]. This instruction code is not defined in the RISC-V spec.

[imphil]

This is referring to reg-reg loads as shown in this older snippet of the file:

ibex/zeroriscy_decoder.sv

Lines 289 to 307 in f7c2b64

	// reg-reg load (different encoding)
	if (instr_rdata_i[14:12] == 3'b111) begin
	// offset from RS2
	alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD;
	// sign/zero extension
	data_sign_extension_o = ~instr_rdata_i[30];
	// load size
	unique case (instr_rdata_i[31:25])
	7'b0000_000,
	7'b0100_000: data_type_o = 2'b10; // LB, LBU
	7'b0001_000,
	7'b0101_000: data_type_o = 2'b01; // LH, LHU
	7'b0010_000: data_type_o = 2'b00; // LW
	default: begin
	illegal_insn_o = 1'b1;
	end

Duplicate of #25