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Peripheral Access Crates for LPC microcontrollers
I've also noticed this: https://crates.io/crates/lpc176x-5x
New and seemingly actively maintained. I think we should remove it from the repository and/or invite the author to join lpc-rs.
I've moved lpc82x-pac into this organization, but I've not integrated it into this repository yet. @rnestler, you mentioned that you moved the other PAC crates here with all their history. Could you do the same for lpc82x-pac?
If it's too much of a hassle, don't bother. I can either figure out how to do it myself, or just copy lpc82x-pac here without the history. Please let me know what you think.
All of the following problems have been fixed. None of them have been reported to NXP so far.
There are two approaches to managing SVD files:
The latter is basically the same as the former, but instead of using diff
and patch
to apply the patches, we use git. The applied patches can then be listed using git log
. The only prerequisite for this is that the vanilla SVD file is committed before the patches are applied.
What are your opinons, @hannobraun and @rnestler? I tend towards the second approach, simply patching the SVD file directly and committing the result. It leads to less work when generating the bindings, since patches have already been applied.
Original issue: lpc-rs/lpc82x-pac#19
According to the user manual, section 18.6.1, there should be a bit called SEL_EXTCLK in the WKT's CTRL register. In the SVD file, that bit is marked as reserved.
I plan to contact NXP about this, but haven't gotten to it yet.
I've reported this issue to NXP: https://community.nxp.com/thread/465465
The USART FCR and IIR registers both live at the same address - one is write-only, the other is read-only. The LPC11UXX crate currently only defines one of those - the iir register - and makes it read-only. The SVD does define both, so I guess this might be an svd2rust issue?
Original issue: lpc-rs/lpc82x-pac#6
The SVD file contains duplicate names that prevent the generated code from being compiled. We address this in this patch, but ideally this should be fixed upstream.
I plan to contact NXP about this, but haven't gotten to it yet.
I've reported the issue to NXP: https://community.nxp.com/thread/465465
According to the user manual, they following fields in SPI.STAT can be read and can be cleared by writing 1
:
In the SVD file, all of them are marked as write-only
.
Thanks for creating this repository, @rnestler! Since you didn't leave any work for me, I figured I'd get in on some bikeshedding :)
I'd prefer it if this repository was just called lpc-pac, for two reasons:
lpc-pac
would be easier to parse.-rs
in the organization name, so having it again in the repository name is redundant.I don't feel that strongly though, so if any of you disagree, feel free to close this issue.
Original issue: lpc-rs/lpc82x-pac#16
The MRT timer has a resolution of 31 bits, but the following registers only specify a width of of 24 bits:
INTVAL
(IVALUE
field)TIMER
(VALUE
field)This needs to be fixed by patching the SVD file, as it causes incorrect behavior. The timer value is truncated when reading to or writing from these fields. To remind me to add that patch, I'm not adding the "upstream" tag until that has been done.
A workaround for this is to bypass the field API by reading/writing the bits directly using the bits
method on the register (not the ones in the field API).
I've reported this issue to NXP: https://community.nxp.com/thread/465465
https://docs.rs/lpc11uxx/0.3.0/lpc11uxx/iocon/pio0_1/struct._MODEW.html#method.inactive
Should we rename inactive
to floating
?
Original issue: lpc-rs/lpc82x-pac#7
According the the user manual, the registers are 8 bits wide, with all but 1 bit reserved. The SVD file specifies them as 1 bit wide, which is wrong. We address this issue with this patch, but ideally this should be fixed upstream.
I plan to contact NXP about this, but haven't gotten to it yet.
I've reported the issue to NXP: https://community.nxp.com/thread/465465
Hey, I'm wondering whether the LPC5500 series is on your radar? I'm currently exploring options for a Cortex-M33 chip. Also in a more roundabout manner, can you share some experiences/war stories on using LPC from Rust? Things like SVD quality, proprietary tooling, vendor support (one can dream), etc.
I can do this myself later, but I'd actually like to invite @david-sawatzke to the lpc-rs organization, so he can do it himself :-)
@david-sawatzke Would you like to join the organization?
@lpc-rs/all Any objections?
Original issue: lpc-rs/lpc82x-pac#12
According to the user manual, PRESETCTRL
should contain the following bits, that are not available in the SVD file:
ADC_RST_N
DMA_RST_N
I plan to contact NXP about this, but haven't gotten to it yet.
I've reported this issue to NXP: https://community.nxp.com/thread/465465
I noticed two directories with binaries commited:
Is that intentional?
If so, when would one want to include binaries or not in a new device?
I'm starting to build the PACs for the (rest) LPC546XX family, but there is still an issue with needing to enable the SRAM banks. I opened an issue over at cortex-m-rt in this regard (#303 but i think that par is missing from the LPC54606-pac crate.
Have you figured out a way to include it?
For register PDRUNCFG, bit SYSOSC_PD, WDTOSC_PD, SYSPLL_PD and ACMP is wrong in svd. It should be be POWERED and POWERED_DOWN, but in svd it's DISABLED and ENABLED, totally flipped.
Original issue: lpc-rs/lpc82x-pac#22
I've reported this issue to NXP: https://community.nxp.com/thread/465465
Original issue: lpc-rs/lpc82x-pac#8
I'm not sure if this is something that should be addressed in the SVD file, but it is a problem for us in so far that the code generated from it compiles only with warnings. We address this in this patch.
As I said, I'm not sure if this needs to be fixed upstream, but as I have to contact NXP about other issues anyway, I'm going to bring it up. The names are weird after all, and it's definitely not intentional, as those names seem to be generated from the human-readable description.
I've reported the issue to NXP: https://community.nxp.com/thread/465465
after discussing it in #75 , we might be able to include the lpc81x pac in here.
there is a lot of differences between the patched 0.2 SVD (0.3? xml says 0.2), and the v1 SVD that is currently in this repository.
As I don't have a board with that MCU, it would be hard to test, and to see what would need to be fixed for a new version of the lpc81x-hal crate as well. @apparentlymart seems to be the owner of the HAL.
I don't think this would be an issue since both the PAC and the HAL have not been updated for a long time (3 and 2 years respectively). current new LPC pacs are on version 0.2.1, so they would not break current version of the hal, which relies on lpc-81x v0.1.0.
if @lucab is fine with moving the lpc81x pac here, that can be done by just publishing the current release (v0.2.1) that is generated by the current files for LPC81x.
It's still available as lpc82x
currently.
All of the following problems have been fixed. None of them have been reported to NXP so far.
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