lpc-rs/lpc82x-pac

OBSOLETE. New repository here: https://github.com/lpc-rs/lpc-pac

lpc82x-pac's Issues

Consider using build script instead of shell script

Currently, the code generation process is managed via a shell script. While this is fine for now, it would be nicer to use a Cargo build script. Especially since that would make it possible to move the code generation logic into a library and reuse that for similar projects.

Update cortex-m-rt dependency

We're not depending on the latest version.

Release crate under new name

I've renamed this repository from lpc82x to lpc82x-pac. PAC stands for Peripheral Access Crate, and the -pac suffix is an emerging standard in the Rust community for these crates.

I need to figure out what to do about the old name. Maybe repurpose it as some kind of alias for lpc82x-hal, or release a new version that just fails to compile with a custom error that explains the situation.

IOCONCLKDIV0 to IOCONCLKDIV5 are missing from SYSCON

Hi!

Thank you for your work! Skip to the next paragraph for the issue!
I also started this project (just a bit before you uploaded it xD), but I did not have the time to create the crate and maintain it since. Also I did not notice, the field size issue. Glad you spotted it!
Soon I am getting to the point slowly when I start programming (custom board design takes some time), so time to prepare the chip crate, this time for real

I did open the generated rust code, and I think this issue stands with it.
LPC824 Glitch Filter Clock Divide Register Issue

Support stable Rust

This crate can only be used with a nightly Rust toolchain.

As of 2017-10-12, here's the list of unstable features that we currently depend on:

• global_asm (documentation, tracking issue)
• macro_reexport (documentation, tracking issue)
• used (documentation, tracking issue)
• const_fn (documentation, tracking issue)

I think the thing to do here is just to wait for the features to be stabilized, or for svd2rust to be updated to not use them anymore. Personally, I don't feel in any hurry here.

Bits missing in PRESETCTRL register

According to the user manual, PRESETCTRL should contain the following bits, that are not available in the SVD file:

• ADC_RST_N
• DMA_RST_N

I plan to contact NXP about this, but haven't gotten to it yet.

Build is broken with latest nightly, if "rt" feature is active

The problem is the macro_reexport feature, which has been removed. There's a pull request for svd2rust that fixes this.

Integrate into lpc-pac

This should be integrated into the lpc-pac repository.

MRT registers have wrong bit range for timer value

The MRT timer has a resolution of 31 bits, but the following registers only specify a width of of 24 bits:

1. INTVAL (IVALUE field)
2. TIMER (VALUE field)

This needs to be fixed by patching the SVD file, as it causes incorrect behavior. The timer value is truncated when reading to or writing from these fields. To remind me to add that patch, I'm not adding the "upstream" tag until that has been done.

A workaround for this is to bypass the field API by reading/writing the bits directly using the bits method on the register (not the ones in the field API).

SVD file contains duplicate names

The SVD file contains duplicate names that prevent the generated code from being compiled. We address this in this patch, but ideally this should be fixed upstream.

I plan to contact NXP about this, but haven't gotten to it yet.

CRP settings are not linked in to elf

When using the device crate or the hal crate, one should specify the memory.x file for the linker script link.x in cortex-m-rt.

I have issues with that, because the CRP feature in these controllers:

• text section should come after 0x300, so _stext needs to be specified in memory.x - update to documentation is needed. It is most likely impossible for user code to be a valid CRP setting, so no harm is done, but for clarity that section should be skipped. If the last bytes are needed in the flash, _stat is unwanted however.
• I had to disable ISP by writing a config word into CRP - 0x2fc - region - it became an ugly hack, modifying the mentioned link.x: adding a crp section before text, and including a linker script in there, that is composed of four BYTE directive - not so happy with it.

I am not very accustomed with linkers, and this should be done maybe in upstream. Just reporting the issue. See LPC82X User Manual - Chapter 25: LPC82x Flash In-System and In-Application Programming for reference
Attaching the files made up the solution. crp.ld is placed in my applications root, beside memory.x
crp_solution.zip

Re-generate code from new SVD files

By building and downloading an LPC822 or LPC824 toolchain using the MCUXpresso SDK Builder, it's possible to gain access to newer versions of the SVD file. The LPC822/LPC824 files that come with the respective toolchains fix all of the problems that I found with the old SVD file, but they also seem to introduce new ones.

To use the new SVD files, the following needs to be done:

• Merge the LPC822/LPC824 files into a single LPC82x file. This is trivial, as the files are essentially identical.
• Review the merged file for regressions compared with the old file. This part is a lot of work, due to the size of the files.
• Fix the regressions in the new file.
• Report regressions to NXP.

I've started this process, but I don't have the time to complete it right now. I plan to get back to it as soon as I can.

SVD file contains names with multiple underscores in a row

I'm not sure if this is something that should be addressed in the SVD file, but it is a problem for us in so far that the code generated from it compiles only with warnings. We address this in this patch.

As I said, I'm not sure if this needs to be fixed upstream, but as I have to contact NXP about other issues anyway, I'm going to bring it up. The names are weird after all, and it's definitely not intentional, as those names seem to be generated from the human-readable description.

SVD file contains wrong size for "B" registers in GPIO_PORT

According the the user manual, the registers are 8 bits wide, with all but 1 bit reserved. The SVD file specifies them as 1 bit wide, which is wrong. We address this issue with this patch, but ideally this should be fixed upstream.

I plan to contact NXP about this, but haven't gotten to it yet.

SEL_EXTCLK missing in WKT's CTRL register

According to the user manual, section 18.6.1, there should be a bit called SEL_EXTCLK in the WKT's CTRL register. In the SVD file, that bit is marked as reserved.

I plan to contact NXP about this, but haven't gotten to it yet.

Update changelog

I'm having problems updating the changelog. Clog doesn't generate anything useful, no matter what parameters I set. I haven't had time to look into it yet.