This project forked from brianworts/legv8_singlecycle_processor
Processor designed using Verilog to perform basic LEGv8 Assembly functions including ADD, STUR, LDUR, and SUB. Utilizes instruction and register memory as well as data storage files.
Processor designed using Verilog to perform basic LEGv8 Assembly functions including ADD, STUR, LDUR, and SUB. Utilizes instruction and register memory as well as data storage files.
Open the project_5.xpr file with Vivado Desighn Suite and run simulation to view result of instructions given in IM.dat file. OR View the "Lab 5 Report.pdf" file
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