M M AA ZZZZZZZZZZZZZZZZZZZZZZZZ EEEEEEEEEEEEEEEEEEE
MM MM AAAA ZZZZZZZZ EEEEEEEEEEEEEEEEEEE
MMMM MMMM AA AA ZZZZZZZZ EEEEE
MMMMMM MMMMMM AAA AAA ZZZZZZZZ EEEEE
MMMMMMMM MMMMMMMM AAAA AAAA ZZZZZZZZ EEEEEEEEEEEEEEEEEEE
MMMM MMMM AAAA AAAA ZZZZZZZZ EEEEEEEEEEEEEEEEEEE
MMMM MMMM AAAAA AAAA AAAAA ZZZZZZZZ EEEEE
MMMM MMMM AAAA AAAA ZZZZZZZZ EEEEE
MMMM MMMM AAAA AAAA ZZZZZZZZZ EEEEEEEEEEEEEEEEEEE
MMMM MMMM AAAAA AAAAA ZZZZZZZZZZZZZZZZZZZZZZZ EEEEEEEEEEEEEEEEEEE
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View Code? Open in Web Editor NEWsimple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)