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transfer-learning-for-oral-cancer-detection-using-microscopic-images

Classifying microscopic oral squamous cells as cancerous or not.

udg-med-p6

udoo-rc-car

A RC Car programmed in Arduino python and terminal

unifmu

A universal mechanism for implementing Functional Mock-up Units (FMUs) in various languages

universitycorner-with-php7.2

upverter-hackathon

YC/Upverter Hackathon

using-matlab-and-simulink-with-hardware

In this repository, you will get access for the presentation, and also the codes for using MATLAB and simulink with Raspbery Pi. The repository contains steps for deploying pre-trained image classification model ResNet50 inside the Raspberry Pi, as well as Simulink models for Pitch shifters, image inversion and many more.

uve

Unified Verification Environment

v-usb

A Firmware-Only USB implementation for Atmel's AVR Microcontrollers

vbd

Generate ASCII text block diagrams from VHDL code

vcd2vec

Transform Verilog VCD file to VEC test file

veda-home-automation

dsofgijnsdoifgbndofsgndfs

ventilator

RespiraWorks open source ventilator monorepo for all systems, hardware and software design. This project is ongoing and incomplete.

veri_2_graph

gate level verilog 2 graph viewer

verilog-automatic

Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3

verilog-pli

Release history of Verilog-Pli

verilog-simulator

A simulator for Verilog written in C++

verilog-testbench

auto generate verilog testbench file

verilog-truth

This will take a truth table that you input in and automagically convert it to the proper Verilog HDL format.

verilogdesign

gui for verilog design

verilogimagemaker

Creates verilog-synthesizable bitmapped graphics from PNG files

verilogscript

VerilogScript is an attempt to make Verilog look more like Python.

verilogtools

Tools for Verilog HDL development.

verilogtools-1

Python tools for processing Verilog files

vhd2vl

vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.

vhdl

vhdl related contents

vhdl-emporium

Collection of Various created VHDL code

vhdl-experiments

VHDL experiments built in GHDL

vhdl-programer

vhdl-reentity

A tool that changes the VHDL code in the project when an entity changes