martinhofigueiredo/pcvlsi

Projeto de Circuitos VLSI

PCVLSI

Projeto de Circuitos VLSI

MultiStage InterConnect Network

       ______               ______         ______         ______               ______   
  X0__|     A|_____________|     A|_______|     A|_______|     A|_____________|     A|__Y0
      |      |             |      |       |      |       |      |             |      |    
      |      |             |      |       |      |       |      |             |      |    
  X1__| 0   B|__         __| 4   B|__   __| 8   B|__   __| 12  B|__         __| 16  B|__Y1
      |______|  \       /  |______|  \ /  |______|  \ /  |______|  \       /  |______|    
       ______    \     /    ______    X    ______    X    ______    \     /    ______     
  X2__|     A|____\___/____|     A|__/ \__|     A|__/ \__|     A|____\___/____|     A|__Y2
      |      |     \ /     |      |       |      |       |      |     \ /     |      |    
      |      |      X      |      |       |      |       |      |      X      |      |    
  X3__| 1   B|__   / \   __| 5   B|_______| 9   B|_______| 13  B|__   / \   __| 17  B|__Y3
      |______|  \ /   \ /  |______|       |______|       |______|  \ /   \ /  |______|    
       ______    X     X    ______         ______         ______    X     X    ______     
  X4__|     A|__/ \   / \__|     A|_______|     A|_______|     A|__/ \   / \__|     A|__Y4
      |      |     \ /     |      |       |      |       |      |     \ /     |      |    
      |      |      X      |      |       |      |       |      |      X      |      |    
  X5__| 2   B|_____/_\_____| 6   B|__   __| 10  B|__   __| 14  B|_____/_\_____| 18  B|__Y5
      |______|    /   \    |______|  \ /  |______|  \ /  |______|    /   \    |______|    
       ______    /     \    ______    X    ______    X    ______    /     \    ______     
  X6__|     A|__/       \__|     A|__/ \__|     A|__/ \__|     A|__/       \__|     A|__Y6
      |      |             |      |       |      |       |      |             |      |    
      |      |             |      |       |      |       |      |             |      |    
  X7__| 3   B|_____________| 7   B|_______| 11  B|_______| 15  B|_____________| 19  B|__Y7
      |______|             |______|       |______|       |______|             |______|  

pcvlsi's Issues

Layout

To be able to change the inner layers of device we used and hierachui

AND e OR

Benes 2x2 [TB]

The Benes 2x2 testbench has two rules:

• fastest (smallest) possible
• Function

Outputs:

• $t_{p_{0,0}}$
• $t_{p_{0,1}}$
• $t_{p_{1,0}}$
• $t_{p_{1,1}}$
• $C_{In}$
• $C_{Out}$

Benes 8x8 [TB]

The transmission gate testbench has two rules:

• fastest (smallest) possible
• Similar delay between S and !S

Outputs:

• $t_{p_{i,j}}\ com\ i.j \in [0,7]$
• $C_{In}$
• $C_{Out}$

Output Multiplexer

To Do:

• Domino Logic Implementation
• Transmission Gates Implementation
• Sizing
• Test

The output multiplexer is 4:1 meaning we need 2 bit to encode all possible

S is a bus S<0:1>

Transmission Gate implementation

Overflow Detection

To make sure there's is not a case of overflow there needs to be a XOR of the input carry and the output carr. If either of them are postive it will be out of the 16 bit range

1B ALU

ALU Construction

Trying to create a 1 Bit Alu made of parametric components so that we can test multiple iterations faster

Basic Description of Alu

Functions:

• Invert Inputs
• AND
• OR
• SUM
• Overflow Detection

ALU Func	Code
AND	0000
OR	0001
add	0010
sub	0110

Components

• #1
• #2
• #3
• #4
• #5

Transmission Gate [TB]

The transmission gate testbench has two rules:

• fastest (smallest) possible
• Similar delay between S and !S

Outputs:

• $t_p$
• $C_{In}$
• $C_{Out}$

Input Inversion

To do:

• Transmission Gates
• Sizing
• Domino Mux
• Test

📓 Notes

If the Control Signal is activated either inputs before the bit reaches the ALU it will have to go through an inverter

Less than Operation

Testing

Must create testbenches so we can simulate the functioning of the circuit

• Full Adder
• ALU 1 Bit
• Multiplexers

Inverter [TB]

The inverter testbench has two rules:

• fastest (smallest) inverter possible
• Balanced Inverter

Outputs:

• $t_p$

Full Adder

Full adder

Component that add A and B together and checks if the value carries to next bit

TO DO:

• Implement P network for SUM
• Implement P network for Cout
• Implement Domino Network
• Implement Domino Enhanced Network
• Sizing
• Test

📓 Refs

https://acadpubl.eu/hub/2018-119-15/1/81.pdf

https://ieeexplore.ieee.org/document/7156419

https://www.researchgate.net/figure/Circuit-diagram-of-a-full-bit-adder-using-the-standard-N-P-domino-logic-50_fig3_321069660

Implementation

Domino CMOS

Sum and CarryOut

Functional Blocks

Inputs:

• A
• B
• Carryin

Outputs

• Sum
• CarryOut

Truth Table

A	B	CarryIn	Sum	CarryOut
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Algebra

$$ Sum(A, B, Cin) = A \oplus B \oplus C_{in} $$

$$ C_{out}(A, B, Cin) = A \cdot B + A \cdot C_{in} + B \cdot C_{in} $$